From nobody Sun Apr 28 22:34:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509455835721693.7635532172942; Tue, 31 Oct 2017 06:17:15 -0700 (PDT) Received: from localhost ([::1]:45649 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WPf-0005nq-4m for importer@patchew.org; Tue, 31 Oct 2017 09:17:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58849) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WKB-0001sq-3B for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9WK4-0006zu-SS for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:23 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e9WK4-0006em-K6 for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:16 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1e9WJr-0007Gi-Rd for qemu-devel@nongnu.org; Tue, 31 Oct 2017 13:11:03 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 31 Oct 2017 13:11:25 +0000 Message-Id: <1509455489-14101-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> References: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 1/5] fix WFI/WFE length in syndrome register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Stefano Stabellini WFI/E are often, but not always, 4 bytes long. When they are, we need to set ARM_EL_IL_SHIFT in the syndrome register. Pass the instruction length to HELPER(wfi), use it to decrement pc appropriately and to pass an is_16bit flag to syn_wfx, which sets ARM_EL_IL_SHIFT if needed. Set dc->insn in both arm_tr_translate_insn and thumb_tr_translate_insn. Signed-off-by: Stefano Stabellini Message-id: alpine.DEB.2.10.1710241055160.574@sstabellini-ThinkPad-X260 [PMM: move setting of dc->insn for Thumb so it is correct for 32 bit insns] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.h | 2 +- target/arm/internals.h | 3 ++- target/arm/op_helper.c | 7 ++++--- target/arm/psci.c | 2 +- target/arm/translate-a64.c | 7 ++++++- target/arm/translate.c | 10 +++++++++- 6 files changed, 23 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 2cf6f74..439d228 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -48,7 +48,7 @@ DEF_HELPER_FLAGS_3(sel_flags, TCG_CALL_NO_RWG_SE, DEF_HELPER_2(exception_internal, void, env, i32) DEF_HELPER_4(exception_with_syndrome, void, env, i32, i32, i32) DEF_HELPER_1(setend, void, env) -DEF_HELPER_1(wfi, void, env) +DEF_HELPER_2(wfi, void, env, i32) DEF_HELPER_1(wfe, void, env) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) diff --git a/target/arm/internals.h b/target/arm/internals.h index 43106a2..d9cc75e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -428,9 +428,10 @@ static inline uint32_t syn_breakpoint(int same_el) | ARM_EL_IL | 0x22; } =20 -static inline uint32_t syn_wfx(int cv, int cond, int ti) +static inline uint32_t syn_wfx(int cv, int cond, int ti, bool is_16bit) { return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | + (is_16bit ? 0 : (1 << ARM_EL_IL_SHIFT)) | (cv << 24) | (cond << 20) | ti; } =20 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 138d0df..a40a84a 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -463,7 +463,7 @@ static inline int check_wfx_trap(CPUARMState *env, bool= is_wfe) return 0; } =20 -void HELPER(wfi)(CPUARMState *env) +void HELPER(wfi)(CPUARMState *env, uint32_t insn_len) { CPUState *cs =3D CPU(arm_env_get_cpu(env)); int target_el =3D check_wfx_trap(env, false); @@ -476,8 +476,9 @@ void HELPER(wfi)(CPUARMState *env) } =20 if (target_el) { - env->pc -=3D 4; - raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0), target_el); + env->pc -=3D insn_len; + raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0, insn_len =3D=3D= 2), + target_el); } =20 cs->exception_index =3D EXCP_HLT; diff --git a/target/arm/psci.c b/target/arm/psci.c index fc34b26..eb7b88e 100644 --- a/target/arm/psci.c +++ b/target/arm/psci.c @@ -189,7 +189,7 @@ void arm_handle_psci_call(ARMCPU *cpu) } else { env->regs[0] =3D 0; } - helper_wfi(env); + helper_wfi(env, 4); break; case QEMU_PSCI_0_1_FN_MIGRATE: case QEMU_PSCI_0_2_FN_MIGRATE: diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e98fbcf..caca05a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11400,17 +11400,22 @@ static void aarch64_tr_tb_stop(DisasContextBase *= dcbase, CPUState *cpu) gen_helper_yield(cpu_env); break; case DISAS_WFI: + { /* This is a special case because we don't want to just halt t= he CPU * if trying to debug across a WFI. */ + TCGv_i32 tmp =3D tcg_const_i32(4); + gen_a64_set_pc_im(dc->pc); - gen_helper_wfi(cpu_env); + gen_helper_wfi(cpu_env, tmp); + tcg_temp_free_i32(tmp); /* The helper doesn't necessarily throw an exception, but we * must go back to the main loop to check for interrupts anywa= y. */ tcg_gen_exit_tb(0); break; } + } } =20 /* Functions above can change dc->pc, so re-align db->pc_next */ diff --git a/target/arm/translate.c b/target/arm/translate.c index 6ba4ae9..df57dbb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12125,6 +12125,7 @@ static void arm_tr_translate_insn(DisasContextBase = *dcbase, CPUState *cpu) } =20 insn =3D arm_ldl_code(env, dc->pc, dc->sctlr_b); + dc->insn =3D insn; dc->pc +=3D 4; disas_arm_insn(dc, insn); =20 @@ -12200,6 +12201,7 @@ static void thumb_tr_translate_insn(DisasContextBas= e *dcbase, CPUState *cpu) insn =3D insn << 16 | insn2; dc->pc +=3D 2; } + dc->insn =3D insn; =20 if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) { uint32_t cond =3D dc->condexec_cond; @@ -12326,12 +12328,18 @@ static void arm_tr_tb_stop(DisasContextBase *dcba= se, CPUState *cpu) /* nothing more to generate */ break; case DISAS_WFI: - gen_helper_wfi(cpu_env); + { + TCGv_i32 tmp =3D tcg_const_i32((dc->thumb && + !(dc->insn & (1U << 31))) ? 2 : = 4); + + gen_helper_wfi(cpu_env, tmp); + tcg_temp_free_i32(tmp); /* The helper doesn't necessarily throw an exception, but we * must go back to the main loop to check for interrupts anywa= y. */ tcg_gen_exit_tb(0); break; + } case DISAS_WFE: gen_helper_wfe(cpu_env); break; --=20 2.7.4 From nobody Sun Apr 28 22:34:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509455905168320.81221541561956; Tue, 31 Oct 2017 06:18:25 -0700 (PDT) Received: from localhost ([::1]:45651 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WQt-0006iA-1I for importer@patchew.org; Tue, 31 Oct 2017 09:18:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58855) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WKD-0001uy-J7 for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9WK3-0006yG-UL for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:25 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e9WK3-0006em-Ns for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:15 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1e9WJs-0007HL-MS for qemu-devel@nongnu.org; Tue, 31 Oct 2017 13:11:04 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 31 Oct 2017 13:11:26 +0000 Message-Id: <1509455489-14101-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> References: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 2/5] xlnx-zcu102: Specify the max number of CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 From: Alistair Francis Specify the number of CPUs that can run on ZynqMP. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 519a16e..e2d15a1 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -240,6 +240,7 @@ static void xlnx_zcu102_machine_class_init(ObjectClass = *oc, void *data) mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; mc->ignore_memory_transaction_failures =3D true; + mc->max_cpus =3D XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; } =20 static const TypeInfo xlnx_zcu102_machine_init_typeinfo =3D { --=20 2.7.4 From nobody Sun Apr 28 22:34:46 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509455589269511.88501211514154; Tue, 31 Oct 2017 06:13:09 -0700 (PDT) Received: from localhost ([::1]:45632 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WLj-0002gX-HD for importer@patchew.org; Tue, 31 Oct 2017 09:12:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58811) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WK4-0001nz-5q for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9WK3-0006we-0R for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:16 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e9WK2-0006em-PF for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:14 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1e9WJt-0007Hr-8X for qemu-devel@nongnu.org; Tue, 31 Oct 2017 13:11:05 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 31 Oct 2017 13:11:27 +0000 Message-Id: <1509455489-14101-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> References: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 3/5] msf2: Remove dead code reported by Coverity X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Subbaraya Sundeep Fixed incorrect frame size mask, validated maximum frame size in spi_write and removed dead code. Signed-off-by: Subbaraya Sundeep Reviewed-by: Darren Kenny Reviewed-by: Alistair Francis Message-id: 1508898544-10307-1-git-send-email-sundeep.lkml@gmail.com Signed-off-by: Peter Maydell --- hw/ssi/mss-spi.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/ssi/mss-spi.c b/hw/ssi/mss-spi.c index 5a8e308..d60daba 100644 --- a/hw/ssi/mss-spi.c +++ b/hw/ssi/mss-spi.c @@ -76,9 +76,10 @@ #define C_BIGFIFO (1 << 29) #define C_RESET (1 << 31) =20 -#define FRAMESZ_MASK 0x1F +#define FRAMESZ_MASK 0x3F #define FMCOUNT_MASK 0x00FFFF00 #define FMCOUNT_SHIFT 8 +#define FRAMESZ_MAX 32 =20 static void txfifo_reset(MSSSpiState *s) { @@ -104,10 +105,8 @@ static void set_fifodepth(MSSSpiState *s) s->fifo_depth =3D 32; } else if (size <=3D 16) { s->fifo_depth =3D 16; - } else if (size <=3D 32) { - s->fifo_depth =3D 8; } else { - s->fifo_depth =3D 4; + s->fifo_depth =3D 8; } } =20 @@ -301,6 +300,17 @@ static void spi_write(void *opaque, hwaddr addr, if (s->enabled) { break; } + /* + * [31:6] bits are reserved bits and for future use. + * [5:0] are for frame size. Only [5:0] bits are validated + * during write, [31:6] bits are untouched. + */ + if ((value & FRAMESZ_MASK) > FRAMESZ_MAX) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Incorrect size %u provided= ." + "Maximum frame size is %u\n", + __func__, value & FRAMESZ_MASK, FRAMESZ_MAX); + break; + } s->regs[R_SPI_DFSIZE] =3D value; break; =20 --=20 2.7.4 From nobody Sun Apr 28 22:34:46 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509455607992523.596767182484; Tue, 31 Oct 2017 06:13:27 -0700 (PDT) Received: from localhost ([::1]:45633 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WLw-0002ol-5b for importer@patchew.org; Tue, 31 Oct 2017 09:13:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58832) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WK7-0001qT-OT for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9WK2-0006v1-2a for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:19 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e9WK1-0006em-RU for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:13 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1e9WJt-0007IH-VM for qemu-devel@nongnu.org; Tue, 31 Oct 2017 13:11:05 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 31 Oct 2017 13:11:28 +0000 Message-Id: <1509455489-14101-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> References: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 4/5] msf2: Wire up SYSRESETREQ in SoC for system reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Subbaraya Sundeep Implemented system reset by creating SYSRESETREQ gpio out from nvic. Signed-off-by: Subbaraya Sundeep Message-id: 1509253165-7434-1-git-send-email-sundeep.lkml@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/msf2-soc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index 6f97fa9..a8ec2cd 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -57,6 +57,13 @@ static const int spi_irq[MSF2_NUM_SPIS] =3D { 2, 3 }; static const int uart_irq[MSF2_NUM_UARTS] =3D { 10, 11 }; static const int timer_irq[MSF2_NUM_TIMERS] =3D { 14, 15 }; =20 +static void do_sys_reset(void *opaque, int n, int level) +{ + if (level) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + } +} + static void m2sxxx_soc_initfn(Object *obj) { MSF2State *s =3D MSF2_SOC(obj); @@ -125,6 +132,10 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, E= rror **errp) error_append_hint(errp, "m3clk can not be zero\n"); return; } + + qdev_connect_gpio_out_named(DEVICE(&s->armv7m.nvic), "SYSRESETREQ", 0, + qemu_allocate_irq(&do_sys_reset, NULL, 0)); + system_clock_scale =3D NANOSECONDS_PER_SECOND / s->m3clk; =20 for (i =3D 0; i < MSF2_NUM_UARTS; i++) { --=20 2.7.4 From nobody Sun Apr 28 22:34:46 2024 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1509455589268692.2000049705488; Tue, 31 Oct 2017 06:13:09 -0700 (PDT) Received: from localhost ([::1]:45631 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WLd-0002dM-50 for importer@patchew.org; Tue, 31 Oct 2017 09:12:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58794) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9WK2-0001nh-3n for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9WK1-0006tP-4u for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:38084) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e9WK0-0006em-TW for qemu-devel@nongnu.org; Tue, 31 Oct 2017 09:11:13 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1e9WJu-0007Ij-LS for qemu-devel@nongnu.org; Tue, 31 Oct 2017 13:11:06 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 31 Oct 2017 13:11:29 +0000 Message-Id: <1509455489-14101-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> References: <1509455489-14101-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 5/5] hw/pci-host/gpex: Improve INTX to gsi routing error checking X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Eric Auger We exposed gpex_set_irq_num() for machines to set the INTx to GSI routing. However if the machine forgets to call that function we currently do not check the association was properly done. Let's initialize gsi values to -1 and if this value is found in gpex_route_intx_pin_to_irq, set the routing mode as disabled. Signed-off-by: Eric Auger Message-id: 1508776211-22175-1-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/pci-host/gpex.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index 4090793..edf305b 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -57,9 +57,14 @@ static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opa= que, int pin) { PCIINTxRoute route; GPEXHost *s =3D opaque; + int gsi =3D s->irq_num[pin]; =20 - route.mode =3D PCI_INTX_ENABLED; - route.irq =3D s->irq_num[pin]; + route.irq =3D gsi; + if (gsi < 0) { + route.mode =3D PCI_INTX_DISABLED; + } else { + route.mode =3D PCI_INTX_ENABLED; + } =20 return route; } @@ -81,6 +86,7 @@ static void gpex_host_realize(DeviceState *dev, Error **e= rrp) sysbus_init_mmio(sbd, &s->io_ioport); for (i =3D 0; i < GPEX_NUM_IRQS; i++) { sysbus_init_irq(sbd, &s->irq[i]); + s->irq_num[i] =3D -1; } =20 pci->bus =3D pci_register_bus(dev, "pcie.0", gpex_set_irq, --=20 2.7.4