From nobody Tue Feb 10 13:34:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507583540697860.5182243813906; Mon, 9 Oct 2017 14:12:20 -0700 (PDT) Received: from localhost ([::1]:59822 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1fLM-0007ci-AU for importer@patchew.org; Mon, 09 Oct 2017 17:12:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56666) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1fGu-0004Fr-Ps for qemu-devel@nongnu.org; Mon, 09 Oct 2017 17:07:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1fGr-0006c8-JB for qemu-devel@nongnu.org; Mon, 09 Oct 2017 17:07:32 -0400 Received: from chuckie.co.uk ([82.165.15.123]:40542 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e1fGr-0006ZN-98 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 17:07:29 -0400 Received: from host109-153-37-179.range109-153.btcentralplus.com ([109.153.37.179] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1e1fGm-0003wf-Q5; Mon, 09 Oct 2017 22:07:26 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Mon, 9 Oct 2017 22:06:56 +0100 Message-Id: <1507583223-14819-2-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1507583223-14819-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1507583223-14819-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.153.37.179 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 1/8] sparc32_dma: rename SPARC32_DMA type to SPARC32_DMA_DEVICE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Also update the function names to match as appropriate. While we're here rename the type from sparc32_dma to sparc32-dma in order to match the current QOM convention. Signed-off-by: Mark Cave-Ayland --- hw/dma/sparc32_dma.c | 67 +++++++++++++++++++++++++---------------------= ---- hw/sparc/sun4m.c | 2 +- 2 files changed, 35 insertions(+), 34 deletions(-) diff --git a/hw/dma/sparc32_dma.c b/hw/dma/sparc32_dma.c index eb491b5..a8d31c1 100644 --- a/hw/dma/sparc32_dma.c +++ b/hw/dma/sparc32_dma.c @@ -61,12 +61,13 @@ /* XXX SCSI and ethernet should have different read-only bit masks */ #define DMA_CSR_RO_MASK 0xfe000007 =20 -#define TYPE_SPARC32_DMA "sparc32_dma" -#define SPARC32_DMA(obj) OBJECT_CHECK(DMAState, (obj), TYPE_SPARC32_DMA) +#define TYPE_SPARC32_DMA_DEVICE "sparc32-dma-device" +#define SPARC32_DMA_DEVICE(obj) OBJECT_CHECK(DMADeviceState, (obj), \ + TYPE_SPARC32_DMA_DEVICE) =20 -typedef struct DMAState DMAState; +typedef struct DMADeviceState DMADeviceState; =20 -struct DMAState { +struct DMADeviceState { SysBusDevice parent_obj; =20 MemoryRegion iomem; @@ -86,7 +87,7 @@ enum { void ledma_memory_read(void *opaque, hwaddr addr, uint8_t *buf, int len, int do_bswap) { - DMAState *s =3D opaque; + DMADeviceState *s =3D opaque; int i; =20 addr |=3D s->dmaregs[3]; @@ -106,7 +107,7 @@ void ledma_memory_read(void *opaque, hwaddr addr, void ledma_memory_write(void *opaque, hwaddr addr, uint8_t *buf, int len, int do_bswap) { - DMAState *s =3D opaque; + DMADeviceState *s =3D opaque; int l, i; uint16_t tmp_buf[32]; =20 @@ -134,7 +135,7 @@ void ledma_memory_write(void *opaque, hwaddr addr, =20 static void dma_set_irq(void *opaque, int irq, int level) { - DMAState *s =3D opaque; + DMADeviceState *s =3D opaque; if (level) { s->dmaregs[0] |=3D DMA_INTR; if (s->dmaregs[0] & DMA_INTREN) { @@ -154,7 +155,7 @@ static void dma_set_irq(void *opaque, int irq, int leve= l) =20 void espdma_memory_read(void *opaque, uint8_t *buf, int len) { - DMAState *s =3D opaque; + DMADeviceState *s =3D opaque; =20 trace_espdma_memory_read(s->dmaregs[1]); sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len); @@ -163,7 +164,7 @@ void espdma_memory_read(void *opaque, uint8_t *buf, int= len) =20 void espdma_memory_write(void *opaque, uint8_t *buf, int len) { - DMAState *s =3D opaque; + DMADeviceState *s =3D opaque; =20 trace_espdma_memory_write(s->dmaregs[1]); sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len); @@ -173,7 +174,7 @@ void espdma_memory_write(void *opaque, uint8_t *buf, in= t len) static uint64_t dma_mem_read(void *opaque, hwaddr addr, unsigned size) { - DMAState *s =3D opaque; + DMADeviceState *s =3D opaque; uint32_t saddr; =20 if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) { @@ -190,7 +191,7 @@ static uint64_t dma_mem_read(void *opaque, hwaddr addr, static void dma_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - DMAState *s =3D opaque; + DMADeviceState *s =3D opaque; uint32_t saddr; =20 if (s->is_ledma && (addr > DMA_MAX_REG_OFFSET)) { @@ -252,28 +253,28 @@ static const MemoryRegionOps dma_mem_ops =3D { }, }; =20 -static void dma_reset(DeviceState *d) +static void sparc32_dma_device_reset(DeviceState *d) { - DMAState *s =3D SPARC32_DMA(d); + DMADeviceState *s =3D SPARC32_DMA_DEVICE(d); =20 memset(s->dmaregs, 0, DMA_SIZE); s->dmaregs[0] =3D DMA_VER; } =20 -static const VMStateDescription vmstate_dma =3D { +static const VMStateDescription vmstate_sparc32_dma_device =3D { .name =3D"sparc32_dma", .version_id =3D 2, .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { - VMSTATE_UINT32_ARRAY(dmaregs, DMAState, DMA_REGS), + VMSTATE_UINT32_ARRAY(dmaregs, DMADeviceState, DMA_REGS), VMSTATE_END_OF_LIST() } }; =20 -static void sparc32_dma_init(Object *obj) +static void sparc32_dma_device_init(Object *obj) { DeviceState *dev =3D DEVICE(obj); - DMAState *s =3D SPARC32_DMA(obj); + DMADeviceState *s =3D SPARC32_DMA_DEVICE(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); =20 sysbus_init_irq(sbd, &s->irq); @@ -284,9 +285,9 @@ static void sparc32_dma_init(Object *obj) qdev_init_gpio_out(dev, s->gpio, 2); } =20 -static void sparc32_dma_realize(DeviceState *dev, Error **errp) +static void sparc32_dma_device_realize(DeviceState *dev, Error **errp) { - DMAState *s =3D SPARC32_DMA(dev); + DMADeviceState *s =3D SPARC32_DMA_DEVICE(dev); int reg_size; =20 reg_size =3D s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE; @@ -294,35 +295,35 @@ static void sparc32_dma_realize(DeviceState *dev, Err= or **errp) "dma", reg_size); } =20 -static Property sparc32_dma_properties[] =3D { - DEFINE_PROP_PTR("iommu_opaque", DMAState, iommu), - DEFINE_PROP_UINT32("is_ledma", DMAState, is_ledma, 0), +static Property sparc32_dma_device_properties[] =3D { + DEFINE_PROP_PTR("iommu_opaque", DMADeviceState, iommu), + DEFINE_PROP_UINT32("is_ledma", DMADeviceState, is_ledma, 0), DEFINE_PROP_END_OF_LIST(), }; =20 -static void sparc32_dma_class_init(ObjectClass *klass, void *data) +static void sparc32_dma_device_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - dc->reset =3D dma_reset; - dc->vmsd =3D &vmstate_dma; - dc->props =3D sparc32_dma_properties; - dc->realize =3D sparc32_dma_realize; + dc->reset =3D sparc32_dma_device_reset; + dc->vmsd =3D &vmstate_sparc32_dma_device; + dc->props =3D sparc32_dma_device_properties; + dc->realize =3D sparc32_dma_device_realize; /* Reason: pointer property "iommu_opaque" */ dc->user_creatable =3D false; } =20 -static const TypeInfo sparc32_dma_info =3D { - .name =3D TYPE_SPARC32_DMA, +static const TypeInfo sparc32_dma_device_info =3D { + .name =3D TYPE_SPARC32_DMA_DEVICE, .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(DMAState), - .instance_init =3D sparc32_dma_init, - .class_init =3D sparc32_dma_class_init, + .instance_size =3D sizeof(DMADeviceState), + .instance_init =3D sparc32_dma_device_init, + .class_init =3D sparc32_dma_device_class_init, }; =20 static void sparc32_dma_register_types(void) { - type_register_static(&sparc32_dma_info); + type_register_static(&sparc32_dma_device_info); } =20 type_init(sparc32_dma_register_types) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index e1bdd48..82c553c 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -313,7 +313,7 @@ static void *sparc32_dma_init(hwaddr daddr, qemu_irq pa= rent_irq, DeviceState *dev; SysBusDevice *s; =20 - dev =3D qdev_create(NULL, "sparc32_dma"); + dev =3D qdev_create(NULL, "sparc32-dma-device"); qdev_prop_set_ptr(dev, "iommu_opaque", iommu); qdev_prop_set_uint32(dev, "is_ledma", is_ledma); qdev_init_nofail(dev); --=20 1.7.10.4