From nobody Tue Feb 10 12:57:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150757987571919.170890250897173; Mon, 9 Oct 2017 13:11:15 -0700 (PDT) Received: from localhost ([::1]:59638 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1eOB-0001p1-B4 for importer@patchew.org; Mon, 09 Oct 2017 16:10:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33881) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1e5j-0003oH-U2 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 15:51:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1e5g-0006hY-LK for qemu-devel@nongnu.org; Mon, 09 Oct 2017 15:51:56 -0400 Received: from mx1.redhat.com ([209.132.183.28]:49668) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e1e5g-0006h0-C5; Mon, 09 Oct 2017 15:51:52 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 51A257E42A; Mon, 9 Oct 2017 19:51:51 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.34.112.60]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0614460604; Mon, 9 Oct 2017 19:51:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 51A257E42A Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; spf=fail smtp.mailfrom=imammedo@redhat.com From: Igor Mammedov To: qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 21:51:10 +0200 Message-Id: <1507578671-158758-24-git-send-email-imammedo@redhat.com> In-Reply-To: <1507578671-158758-1-git-send-email-imammedo@redhat.com> References: <1507578671-158758-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Mon, 09 Oct 2017 19:51:51 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v2 23/24] ppc: pnv: drop PnvChipClass::cpu_model field X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:ppce500" , "Edgar E. Iglesias" , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" deduce core type directly from chip type instead of maintaining type mapping in PnvChipClass::cpu_model. Signed-off-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- v2: - fix typo: s/pvn_chip_core_typename/pnv_chip_core_typename/ --- include/hw/ppc/pnv.h | 1 - include/hw/ppc/pnv_core.h | 1 - hw/ppc/pnv.c | 25 +++++++++++++------------ hw/ppc/pnv_core.c | 5 ----- 4 files changed, 13 insertions(+), 19 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index d82eee1..20244da 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -69,7 +69,6 @@ typedef struct PnvChipClass { SysBusDeviceClass parent_class; =20 /*< public >*/ - const char *cpu_model; PnvChipType chip_type; uint64_t chip_cfam_id; uint64_t cores_mask; diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index a336a1f..e337af7 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -46,6 +46,5 @@ typedef struct PnvCoreClass { =20 #define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE #define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX -extern char *pnv_core_typename(const char *model); =20 #endif /* _PPC_PNV_CORE_H */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 3eafa28..80c7f62 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -55,6 +55,16 @@ #define KERNEL_LOAD_ADDR 0x20000000 #define INITRD_LOAD_ADDR 0x40000000 =20 +static const char *pnv_chip_core_typename(const PnvChip *o) +{ + const char *chip_type =3D object_class_get_name(object_get_class(OBJEC= T(o))); + int len =3D strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); + char *s =3D g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type= ); + const char *core_type =3D object_class_get_name(object_class_by_name(s= )); + g_free(s); + return core_type; +} + /* * On Power Systems E880 (POWER8), the max cpus (threads) should be : * 4 * 4 sockets * 12 cores * 8 threads =3D 1536 @@ -269,8 +279,7 @@ static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt) =20 static void powernv_populate_chip(PnvChip *chip, void *fdt) { - PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); - char *typename =3D pnv_core_typename(pcc->cpu_model); + const char *typename =3D pnv_chip_core_typename(chip); size_t typesize =3D object_type_get_instance_size(typename); int i; =20 @@ -300,7 +309,6 @@ static void powernv_populate_chip(PnvChip *chip, void *= fdt) powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start, chip->ram_size); } - g_free(typename); } =20 static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off) @@ -712,7 +720,6 @@ static void pnv_chip_power8e_class_init(ObjectClass *kl= ass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->cpu_model =3D "power8e_v2.1"; k->chip_type =3D PNV_CHIP_POWER8E; k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ k->cores_mask =3D POWER8E_CORE_MASK; @@ -734,7 +741,6 @@ static void pnv_chip_power8_class_init(ObjectClass *kla= ss, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->cpu_model =3D "power8_v2.0"; k->chip_type =3D PNV_CHIP_POWER8; k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ k->cores_mask =3D POWER8_CORE_MASK; @@ -756,7 +762,6 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *= klass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->cpu_model =3D "power8nvl_v1.0"; k->chip_type =3D PNV_CHIP_POWER8NVL; k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ k->cores_mask =3D POWER8_CORE_MASK; @@ -778,7 +783,6 @@ static void pnv_chip_power9_class_init(ObjectClass *kla= ss, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->cpu_model =3D "power9_v1.0"; k->chip_type =3D PNV_CHIP_POWER9; k->chip_cfam_id =3D 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ k->cores_mask =3D POWER9_CORE_MASK; @@ -853,7 +857,7 @@ static void pnv_chip_init(Object *obj) static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) { PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); - char *typename =3D pnv_core_typename(pcc->cpu_model); + const char *typename =3D pnv_chip_core_typename(chip); size_t typesize =3D object_type_get_instance_size(typename); int i, j; char *name; @@ -878,8 +882,6 @@ static void pnv_chip_icp_realize(PnvChip *chip, Error *= *errp) memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->= mmio); } } - - g_free(typename); } =20 static void pnv_chip_realize(DeviceState *dev, Error **errp) @@ -887,7 +889,7 @@ static void pnv_chip_realize(DeviceState *dev, Error **= errp) PnvChip *chip =3D PNV_CHIP(dev); Error *error =3D NULL; PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); - char *typename =3D pnv_core_typename(pcc->cpu_model); + const char *typename =3D pnv_chip_core_typename(chip); size_t typesize =3D object_type_get_instance_size(typename); int i, core_hwid; =20 @@ -946,7 +948,6 @@ static void pnv_chip_realize(DeviceState *dev, Error **= errp) &PNV_CORE(pnv_core)->xscom_regs); i++; } - g_free(typename); =20 /* Create LPC controller */ object_property_set_bool(OBJECT(&chip->lpc), true, "realized", diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 438dbd1..71eb90a 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -246,9 +246,4 @@ static const TypeInfo pnv_core_infos[] =3D { DEFINE_PNV_CORE_TYPE("power9_v1.0"), }; =20 -char *pnv_core_typename(const char *model) -{ - return g_strdup_printf(PNV_CORE_TYPE_NAME("%s"), model); -} - DEFINE_TYPES(pnv_core_infos) --=20 2.7.4