From nobody Mon Nov 3 08:19:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507557274120329.0227371081646; Mon, 9 Oct 2017 06:54:34 -0700 (PDT) Received: from localhost ([::1]:58026 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1YVj-00055y-NI for importer@patchew.org; Mon, 09 Oct 2017 09:54:23 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43528) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e1YQT-0001MS-56 for qemu-devel@nongnu.org; Mon, 09 Oct 2017 09:48:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e1YQS-0004A3-2d for qemu-devel@nongnu.org; Mon, 09 Oct 2017 09:48:57 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37778) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e1YQM-0003zX-QK; Mon, 09 Oct 2017 09:48:50 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1e1YQD-0004YK-C3; Mon, 09 Oct 2017 14:48:41 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 9 Oct 2017 14:48:35 +0100 Message-Id: <1507556919-24992-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507556919-24992-1-git-send-email-peter.maydell@linaro.org> References: <1507556919-24992-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 5/9] target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The code which implements the Thumb1 split BL/BLX instructions is guarded by a check on "not M or THUMB2". All we really need to check here is "not THUMB2" (and we assume that elsewhere too, eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns). This doesn't change behaviour because all M profile cores have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2. (v6M implements a very restricted subset of Thumb2, but we can cross that bridge when we get to it with appropriate feature bits.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 58d706c..f5ca87f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9722,8 +9722,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasC= ontext *s, uint16_t insn_hw int conds; int logic_cc; =20 - if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2) - || arm_dc_feature(s, ARM_FEATURE_M))) { + if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) { /* Thumb-1 cores may need to treat bl and blx as a pair of 16-bit instructions to get correct prefetch abort behavior. */ insn =3D insn_hw1; --=20 2.7.4