From nobody Tue Apr 15 17:10:27 2025 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507308530451333.80771981728253; Fri, 6 Oct 2017 09:48:50 -0700 (PDT) Received: from localhost ([::1]:45943 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e0Vnc-0005Kj-EK for importer@patchew.org; Fri, 06 Oct 2017 12:48:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58109) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e0V1l-0004E1-FN for qemu-devel@nongnu.org; Fri, 06 Oct 2017 11:59:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e0V1j-0007oW-U6 for qemu-devel@nongnu.org; Fri, 06 Oct 2017 11:59:05 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37718) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e0V1j-0007nY-Mq for qemu-devel@nongnu.org; Fri, 06 Oct 2017 11:59:03 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1e0V1i-0002yf-Gb for qemu-devel@nongnu.org; Fri, 06 Oct 2017 16:59:02 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 6 Oct 2017 16:59:43 +0100 Message-Id: <1507305585-20608-19-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507305585-20608-1-git-send-email-peter.maydell@linaro.org> References: <1507305585-20608-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 18/20] target/arm: Fix calculation of secure mm_idx values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_6 Z_629925259 SPT_0 In cpu_mmu_index() we try to do this: if (env->v7m.secure) { mmu_idx +=3D ARMMMUIdx_MSUser; } but it will give the wrong answer, because ARMMMUIdx_MSUser includes the 0x40 ARM_MMU_IDX_M field, and so does the mmu_idx we're adding to, and we'll end up with 0x8n rather than 0x4n. This error is then nullified by the call to arm_to_core_mmu_idx() which masks out the high part, but we're about to factor out the code that calculates the ARMMMUIdx values so it can be used without passing it through arm_to_core_mmu_idx(), so fix this bug first. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 1506092407-26985-16-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 441e584..70c1f85 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2335,14 +2335,16 @@ static inline int cpu_mmu_index(CPUARMState *env, b= ool ifetch) int el =3D arm_current_el(env); =20 if (arm_feature(env, ARM_FEATURE_M)) { - ARMMMUIdx mmu_idx =3D el =3D=3D 0 ? ARMMMUIdx_MUser : ARMMMUIdx_MP= riv; + ARMMMUIdx mmu_idx; =20 - if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) { - mmu_idx =3D ARMMMUIdx_MNegPri; + if (el =3D=3D 0) { + mmu_idx =3D env->v7m.secure ? ARMMMUIdx_MSUser : ARMMMUIdx_MUs= er; + } else { + mmu_idx =3D env->v7m.secure ? ARMMMUIdx_MSPriv : ARMMMUIdx_MPr= iv; } =20 - if (env->v7m.secure) { - mmu_idx +=3D ARMMMUIdx_MSUser; + if (armv7m_nvic_neg_prio_requested(env->nvic, env->v7m.secure)) { + mmu_idx =3D env->v7m.secure ? ARMMMUIdx_MSNegPri : ARMMMUIdx_M= NegPri; } =20 return arm_to_core_mmu_idx(mmu_idx); --=20 2.7.4