From nobody Tue Apr 15 17:06:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1507307614738835.4012976231372; Fri, 6 Oct 2017 09:33:34 -0700 (PDT) Received: from localhost ([::1]:45810 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e0VZ8-0000W4-0U for importer@patchew.org; Fri, 06 Oct 2017 12:33:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58154) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e0V1m-0004FK-Nm for qemu-devel@nongnu.org; Fri, 06 Oct 2017 11:59:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e0V1i-0007n8-Mn for qemu-devel@nongnu.org; Fri, 06 Oct 2017 11:59:06 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37712) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1e0V1i-0007eF-EE for qemu-devel@nongnu.org; Fri, 06 Oct 2017 11:59:02 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1e0V1e-0002vn-5F for qemu-devel@nongnu.org; Fri, 06 Oct 2017 16:58:58 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Fri, 6 Oct 2017 16:59:36 +0100 Message-Id: <1507305585-20608-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507305585-20608-1-git-send-email-peter.maydell@linaro.org> References: <1507305585-20608-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/20] target/arm: Don't warn about exception return with PC low bit set for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 In the v8M architecture, return from an exception to a PC which has bit 0 set is not UNPREDICTABLE; it is defined that bit 0 is discarded [R_HRJH]. Restrict our complaint about this to v7M. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 1506092407-26985-9-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index bb57be7..c7cf24c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6431,16 +6431,24 @@ static void do_v7m_exception_exit(ARMCPU *cpu) env->regs[12] =3D ldl_phys(cs->as, frameptr + 0x10); env->regs[14] =3D ldl_phys(cs->as, frameptr + 0x14); env->regs[15] =3D ldl_phys(cs->as, frameptr + 0x18); + + /* Returning from an exception with a PC with bit 0 set is defined + * behaviour on v8M (bit 0 is ignored), but for v7M it was specifi= ed + * to be UNPREDICTABLE. In practice actual v7M hardware seems to i= gnore + * the lsbit, and there are several RTOSes out there which incorre= ctly + * assume the r15 in the stack frame should be a Thumb-style "lsbit + * indicates ARM/Thumb" value, so ignore the bit on v7M as well, b= ut + * complain about the badly behaved guest. + */ if (env->regs[15] & 1) { - qemu_log_mask(LOG_GUEST_ERROR, - "M profile return from interrupt with misaligned= " - "PC is UNPREDICTABLE\n"); - /* Actual hardware seems to ignore the lsbit, and there are se= veral - * RTOSes out there which incorrectly assume the r15 in the st= ack - * frame should be a Thumb-style "lsbit indicates ARM/Thumb" v= alue. - */ env->regs[15] &=3D ~1U; + if (!arm_feature(env, ARM_FEATURE_V8)) { + qemu_log_mask(LOG_GUEST_ERROR, + "M profile return from interrupt with misali= gned " + "PC is UNPREDICTABLE on v7M\n"); + } } + xpsr =3D ldl_phys(cs->as, frameptr + 0x1c); =20 if (arm_feature(env, ARM_FEATURE_V8)) { --=20 2.7.4