From nobody Thu Dec 18 17:55:21 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 150601220494768.92026180220694; Thu, 21 Sep 2017 09:43:24 -0700 (PDT) Received: from localhost ([::1]:54635 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dv4ZG-0004Ps-FI for importer@patchew.org; Thu, 21 Sep 2017 12:43:14 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60149) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dv4XK-00032Q-FJ for qemu-devel@nongnu.org; Thu, 21 Sep 2017 12:41:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dv4XJ-0002pa-E1 for qemu-devel@nongnu.org; Thu, 21 Sep 2017 12:41:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37496) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dv4XJ-0002la-6p for qemu-devel@nongnu.org; Thu, 21 Sep 2017 12:41:13 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dv4XI-000585-6A for qemu-devel@nongnu.org; Thu, 21 Sep 2017 17:41:12 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 21 Sep 2017 17:41:22 +0100 Message-Id: <1506012099-13605-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506012099-13605-1-git-send-email-peter.maydell@linaro.org> References: <1506012099-13605-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 14/31] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If AIRCR.BFHFNMINS is clear, then although NonSecure HardFault can still be pended via SHCSR.HARDFAULTPENDED it mustn't actually preempt execution. The simple way to achieve this is to clear the enable bit for it, since the enable bit isn't guest visible. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1505240046-11454-15-git-send-email-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 0c1d591..35225c8 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -937,11 +937,16 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, (R_V7M_AIRCR_SYSRESETREQS_MASK | R_V7M_AIRCR_BFHFNMINS_MASK | R_V7M_AIRCR_PRIS_MASK); - /* BFHFNMINS changes the priority of Secure HardFault */ + /* BFHFNMINS changes the priority of Secure HardFault, and + * allows a pending Non-secure HardFault to preempt (which + * we implement by marking it enabled). + */ if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { s->sec_vectors[ARMV7M_EXCP_HARD].prio =3D -3; + s->vectors[ARMV7M_EXCP_HARD].enabled =3D 1; } else { s->sec_vectors[ARMV7M_EXCP_HARD].prio =3D -1; + s->vectors[ARMV7M_EXCP_HARD].enabled =3D 0; } } nvic_irq_update(s); @@ -1566,7 +1571,6 @@ static void armv7m_nvic_reset(DeviceState *dev) NVICState *s =3D NVIC(dev); =20 s->vectors[ARMV7M_EXCP_NMI].enabled =3D 1; - s->vectors[ARMV7M_EXCP_HARD].enabled =3D 1; /* MEM, BUS, and USAGE are enabled through * the System Handler Control register */ @@ -1588,6 +1592,10 @@ static void armv7m_nvic_reset(DeviceState *dev) =20 /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC= ) */ s->sec_vectors[ARMV7M_EXCP_HARD].prio =3D -1; + /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */ + s->vectors[ARMV7M_EXCP_HARD].enabled =3D 0; + } else { + s->vectors[ARMV7M_EXCP_HARD].enabled =3D 1; } =20 /* Strictly speaking the reset handler should be enabled. --=20 2.7.4