From nobody Mon Nov 3 20:38:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1506001333738273.19725949296935; Thu, 21 Sep 2017 06:42:13 -0700 (PDT) Received: from localhost ([::1]:53783 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dv1k4-0001ti-W1 for importer@patchew.org; Thu, 21 Sep 2017 09:42:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dv1gg-0007iY-Ia for qemu-devel@nongnu.org; Thu, 21 Sep 2017 09:38:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dv1ga-0006rB-Py for qemu-devel@nongnu.org; Thu, 21 Sep 2017 09:38:42 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:24141) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dv1ga-0006qZ-Ja for qemu-devel@nongnu.org; Thu, 21 Sep 2017 09:38:36 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id C5CFE62AFD3DB; Thu, 21 Sep 2017 14:38:31 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 21 Sep 2017 14:38:34 +0100 From: Yongbok Kim To: Date: Thu, 21 Sep 2017 14:38:11 +0100 Message-ID: <1506001091-8296-8-git-send-email-yongbok.kim@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1506001091-8296-1-git-send-email-yongbok.kim@imgtec.com> References: <1506001091-8296-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 7/7] mips: Improve macro parenthesization X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Eric Blake Although none of the existing macro call-sites were broken, it's always better to write macros that properly parenthesize arguments that can be complex expressions, so that the intended order of operations is not broken. Signed-off-by: Eric Blake Reviewed-by: Yongbok Kim Signed-off-by: Yongbok Kim --- target/mips/dsp_helper.c | 56 ++++++++++++++++++++++++--------------------= ---- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/target/mips/dsp_helper.c b/target/mips/dsp_helper.c index dc70793..f152fea 100644 --- a/target/mips/dsp_helper.c +++ b/target/mips/dsp_helper.c @@ -45,9 +45,9 @@ typedef union { } DSP64Value; =20 /*** MIPS DSP internal functions begin ***/ -#define MIPSDSP_ABS(x) (((x) >=3D 0) ? x : -x) -#define MIPSDSP_OVERFLOW_ADD(a, b, c, d) (~(a ^ b) & (a ^ c) & d) -#define MIPSDSP_OVERFLOW_SUB(a, b, c, d) ((a ^ b) & (a ^ c) & d) +#define MIPSDSP_ABS(x) (((x) >=3D 0) ? (x) : -(x)) +#define MIPSDSP_OVERFLOW_ADD(a, b, c, d) (~((a) ^ (b)) & ((a) ^ (c)) & (d)) +#define MIPSDSP_OVERFLOW_SUB(a, b, c, d) (((a) ^ (b)) & ((a) ^ (c)) & (d)) =20 static inline void set_DSPControl_overflow_flag(uint32_t flag, int positio= n, CPUMIPSState *env) @@ -1047,47 +1047,47 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, u= int32_t b) =20 #define MIPSDSP_SPLIT32_8(num, a, b, c, d) \ do { \ - a =3D (num >> 24) & MIPSDSP_Q0; \ - b =3D (num >> 16) & MIPSDSP_Q0; \ - c =3D (num >> 8) & MIPSDSP_Q0; \ - d =3D num & MIPSDSP_Q0; \ + a =3D ((num) >> 24) & MIPSDSP_Q0; \ + b =3D ((num) >> 16) & MIPSDSP_Q0; \ + c =3D ((num) >> 8) & MIPSDSP_Q0; \ + d =3D (num) & MIPSDSP_Q0; \ } while (0) =20 #define MIPSDSP_SPLIT32_16(num, a, b) \ do { \ - a =3D (num >> 16) & MIPSDSP_LO; \ - b =3D num & MIPSDSP_LO; \ + a =3D ((num) >> 16) & MIPSDSP_LO; \ + b =3D (num) & MIPSDSP_LO; \ } while (0) =20 -#define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \ - (((uint32_t)a << 24) | \ - (((uint32_t)b << 16) | \ - (((uint32_t)c << 8) | \ - ((uint32_t)d & 0xFF))))) -#define MIPSDSP_RETURN32_16(a, b) ((target_long)(int32_t) \ - (((uint32_t)a << 16) | \ - ((uint32_t)b & 0xFFFF))) +#define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \ + (((uint32_t)(a) << 24) | \ + ((uint32_t)(b) << 16) | \ + ((uint32_t)(c) << 8) | \ + ((uint32_t)(d) & 0xFF))) +#define MIPSDSP_RETURN32_16(a, b) ((target_long)(int32_t) \ + (((uint32_t)(a) << 16) | \ + ((uint32_t)(b) & 0xFFFF))) =20 #ifdef TARGET_MIPS64 #define MIPSDSP_SPLIT64_16(num, a, b, c, d) \ do { \ - a =3D (num >> 48) & MIPSDSP_LO; \ - b =3D (num >> 32) & MIPSDSP_LO; \ - c =3D (num >> 16) & MIPSDSP_LO; \ - d =3D num & MIPSDSP_LO; \ + a =3D ((num) >> 48) & MIPSDSP_LO; \ + b =3D ((num) >> 32) & MIPSDSP_LO; \ + c =3D ((num) >> 16) & MIPSDSP_LO; \ + d =3D (num) & MIPSDSP_LO; \ } while (0) =20 #define MIPSDSP_SPLIT64_32(num, a, b) \ do { \ - a =3D (num >> 32) & MIPSDSP_LLO; \ - b =3D num & MIPSDSP_LLO; \ + a =3D ((num) >> 32) & MIPSDSP_LLO; \ + b =3D (num) & MIPSDSP_LLO; \ } while (0) =20 -#define MIPSDSP_RETURN64_16(a, b, c, d) (((uint64_t)a << 48) | \ - ((uint64_t)b << 32) | \ - ((uint64_t)c << 16) | \ - (uint64_t)d) -#define MIPSDSP_RETURN64_32(a, b) (((uint64_t)a << 32) | (uint64_t)b) +#define MIPSDSP_RETURN64_16(a, b, c, d) (((uint64_t)(a) << 48) | \ + ((uint64_t)(b) << 32) | \ + ((uint64_t)(c) << 16) | \ + (uint64_t)(d)) +#define MIPSDSP_RETURN64_32(a, b) (((uint64_t)(a) << 32) | (uint64_t= )(b)) #endif =20 /** DSP Arithmetic Sub-class insns **/ --=20 2.7.4