From nobody Thu Dec 18 17:50:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505411678563338.5056220207845; Thu, 14 Sep 2017 10:54:38 -0700 (PDT) Received: from localhost ([::1]:49182 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYLV-0000zX-24 for importer@patchew.org; Thu, 14 Sep 2017 13:54:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46391) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJW-00084d-MF for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJV-0007ut-Kn for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:34 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJV-0007iP-DM for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:33 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJN-0005n5-8C for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:25 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:36 +0100 Message-Id: <1505411573-27848-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/18] target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Use a symbolic constant M_REG_NUM_BANKS for the array size for registers which are banked by M profile security state, rather than hardcoding lots of 2s. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 1505137930-13255-2-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 98b9b26..5a1f957 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -81,8 +81,11 @@ * accessed via env->registerfield[env->v7m.secure] (whether the security * extension is implemented or not). */ -#define M_REG_NS 0 -#define M_REG_S 1 +enum { + M_REG_NS =3D 0, + M_REG_S =3D 1, + M_REG_NUM_BANKS =3D 2, +}; =20 /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 @@ -433,19 +436,19 @@ typedef struct CPUARMState { uint32_t other_sp; uint32_t other_ss_msp; uint32_t other_ss_psp; - uint32_t vecbase[2]; - uint32_t basepri[2]; - uint32_t control[2]; - uint32_t ccr[2]; /* Configuration and Control */ - uint32_t cfsr[2]; /* Configurable Fault Status */ + uint32_t vecbase[M_REG_NUM_BANKS]; + uint32_t basepri[M_REG_NUM_BANKS]; + uint32_t control[M_REG_NUM_BANKS]; + uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ + uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ - uint32_t mmfar[2]; /* MemManage Fault Address */ + uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ - unsigned mpu_ctrl[2]; /* MPU_CTRL */ + unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ int exception; - uint32_t primask[2]; - uint32_t faultmask[2]; + uint32_t primask[M_REG_NUM_BANKS]; + uint32_t faultmask[M_REG_NUM_BANKS]; uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; =20 @@ -546,7 +549,7 @@ typedef struct CPUARMState { uint32_t *drbar; uint32_t *drsr; uint32_t *dracr; - uint32_t rnr[2]; + uint32_t rnr[M_REG_NUM_BANKS]; } pmsav7; =20 /* PMSAv8 MPU */ @@ -556,10 +559,10 @@ typedef struct CPUARMState { * pmsav7.rnr (region number register) * pmsav7_dregion (number of configured regions) */ - uint32_t *rbar[2]; - uint32_t *rlar[2]; - uint32_t mair0[2]; - uint32_t mair1[2]; + uint32_t *rbar[M_REG_NUM_BANKS]; + uint32_t *rlar[M_REG_NUM_BANKS]; + uint32_t mair0[M_REG_NUM_BANKS]; + uint32_t mair1[M_REG_NUM_BANKS]; } pmsav8; =20 void *nvic; --=20 2.7.4