From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505411678563338.5056220207845; Thu, 14 Sep 2017 10:54:38 -0700 (PDT) Received: from localhost ([::1]:49182 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYLV-0000zX-24 for importer@patchew.org; Thu, 14 Sep 2017 13:54:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46391) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJW-00084d-MF for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJV-0007ut-Kn for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:34 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJV-0007iP-DM for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:33 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJN-0005n5-8C for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:25 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:36 +0100 Message-Id: <1505411573-27848-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 01/18] target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Use a symbolic constant M_REG_NUM_BANKS for the array size for registers which are banked by M profile security state, rather than hardcoding lots of 2s. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 1505137930-13255-2-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 98b9b26..5a1f957 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -81,8 +81,11 @@ * accessed via env->registerfield[env->v7m.secure] (whether the security * extension is implemented or not). */ -#define M_REG_NS 0 -#define M_REG_S 1 +enum { + M_REG_NS =3D 0, + M_REG_S =3D 1, + M_REG_NUM_BANKS =3D 2, +}; =20 /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 @@ -433,19 +436,19 @@ typedef struct CPUARMState { uint32_t other_sp; uint32_t other_ss_msp; uint32_t other_ss_psp; - uint32_t vecbase[2]; - uint32_t basepri[2]; - uint32_t control[2]; - uint32_t ccr[2]; /* Configuration and Control */ - uint32_t cfsr[2]; /* Configurable Fault Status */ + uint32_t vecbase[M_REG_NUM_BANKS]; + uint32_t basepri[M_REG_NUM_BANKS]; + uint32_t control[M_REG_NUM_BANKS]; + uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ + uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ - uint32_t mmfar[2]; /* MemManage Fault Address */ + uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ - unsigned mpu_ctrl[2]; /* MPU_CTRL */ + unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ int exception; - uint32_t primask[2]; - uint32_t faultmask[2]; + uint32_t primask[M_REG_NUM_BANKS]; + uint32_t faultmask[M_REG_NUM_BANKS]; uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; =20 @@ -546,7 +549,7 @@ typedef struct CPUARMState { uint32_t *drbar; uint32_t *drsr; uint32_t *dracr; - uint32_t rnr[2]; + uint32_t rnr[M_REG_NUM_BANKS]; } pmsav7; =20 /* PMSAv8 MPU */ @@ -556,10 +559,10 @@ typedef struct CPUARMState { * pmsav7.rnr (region number register) * pmsav7_dregion (number of configured regions) */ - uint32_t *rbar[2]; - uint32_t *rlar[2]; - uint32_t mair0[2]; - uint32_t mair1[2]; + uint32_t *rbar[M_REG_NUM_BANKS]; + uint32_t *rlar[M_REG_NUM_BANKS]; + uint32_t mair0[M_REG_NUM_BANKS]; + uint32_t mair1[M_REG_NUM_BANKS]; } pmsav8; =20 void *nvic; --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505412686357689.5592686426409; Thu, 14 Sep 2017 11:11:26 -0700 (PDT) Received: from localhost ([::1]:49298 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYbl-0004SU-I1 for importer@patchew.org; Thu, 14 Sep 2017 14:11:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46603) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJc-00088Z-GZ for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJb-00083Z-Do for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:40 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37368) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJb-0007x0-5h for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJN-0005nI-TW for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:25 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:37 +0100 Message-Id: <1505411573-27848-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 02/18] target/arm: Clear exclusive monitor on v7M reset, exception entry/exit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For M profile we must clear the exclusive monitor on reset, exception entry and exception exit. We weren't doing any of these things; fix this bug. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 1505137930-13255-3-git-send-email-peter.maydell@linaro.org --- target/arm/internals.h | 10 ++++++++++ target/arm/cpu.c | 6 ++++++ target/arm/helper.c | 2 ++ target/arm/op_helper.c | 2 +- 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 5d7f24c..a315354 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -444,6 +444,16 @@ void arm_handle_psci_call(ARMCPU *cpu); #endif =20 /** + * arm_clear_exclusive: clear the exclusive monitor + * @env: CPU env + * Clear the CPU's exclusive monitor, like the guest CLREX instruction. + */ +static inline void arm_clear_exclusive(CPUARMState *env) +{ + env->exclusive_addr =3D -1; +} + +/** * ARMMMUFaultInfo: Information describing an ARM MMU Fault * @s2addr: Address that caused a fault at stage 2 * @stage2: True if we faulted at stage 2 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a1acce3..412e94c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -235,6 +235,12 @@ static void arm_cpu_reset(CPUState *s) env->regs[15] =3D 0xFFFF0000; } =20 + /* M profile requires that reset clears the exclusive monitor; + * A profile does not, but clearing it makes more sense than having it + * set with an exclusive access on address zero. + */ + arm_clear_exclusive(env); + env->vfp.xregs[ARM_VFP_FPEXC] =3D 0; #endif =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 329e517..668e367 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6175,6 +6175,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t= lr) =20 armv7m_nvic_acknowledge_irq(env->nvic); switch_v7m_sp(env, 0); + arm_clear_exclusive(env); /* Clear IT bits */ env->condexec_bits =3D 0; env->regs[14] =3D lr; @@ -6354,6 +6355,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } =20 /* Otherwise, we have a successful exception exit. */ + arm_clear_exclusive(env); qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); } =20 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index d1bca46..6a60464 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1022,7 +1022,7 @@ void HELPER(exception_return)(CPUARMState *env) =20 aarch64_save_sp(env, cur_el); =20 - env->exclusive_addr =3D -1; + arm_clear_exclusive(env); =20 /* We must squash the PSTATE.SS bit to zero unless both of the * following hold: --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505412617733192.65723305940605; Thu, 14 Sep 2017 11:10:17 -0700 (PDT) Received: from localhost ([::1]:49291 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYae-0003eD-Kd for importer@patchew.org; Thu, 14 Sep 2017 14:10:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46591) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJc-00088P-9P for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJb-00083i-EE for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:40 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJb-0007iP-5b for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJO-0005o6-O3 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:26 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:38 +0100 Message-Id: <1505411573-27848-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 03/18] target/arm: Get PRECISERR and IBUSERR the right way round X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For a bus fault, the M profile BFSR bit PRECISERR means a bus fault on a data access, and IBUSERR means a bus fault on an instruction access. We had these the wrong way around; fix this. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 1505137930-13255-4-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 668e367..1741e0d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6430,15 +6430,15 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) case 0x8: /* External Abort */ switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: - env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_PRECISERR_MASK; - qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n"); + env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_IBUSERR_MASK; + qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n"); break; case EXCP_DATA_ABORT: env->v7m.cfsr[M_REG_NS] |=3D - (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK); + (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK= ); env->v7m.bfar =3D env->exception.vaddress; qemu_log_mask(CPU_LOG_INT, - "...with CFSR.IBUSERR and BFAR 0x%x\n", + "...with CFSR.PRECISERR and BFAR 0x%x\n", env->v7m.bfar); break; } --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15054118563591004.3889612602878; Thu, 14 Sep 2017 10:57:36 -0700 (PDT) Received: from localhost ([::1]:49198 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYON-0004mc-Ib for importer@patchew.org; Thu, 14 Sep 2017 13:57:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46581) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJc-00088B-1L for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJa-00082M-U3 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:40 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37370) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJa-0007yZ-MW for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJP-0005oX-CQ for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:27 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:39 +0100 Message-Id: <1505411573-27848-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 04/18] nvic: Don't apply group priority mask to negative priorities X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In several places we were unconditionally applying the nvic_gprio_mask() to a priority value. This is incorrect if the priority is one of the fixed negative priority values (for NMI and HardFault), so don't do it. This bug would have caused both NMI and HardFault to be considered as the same priority and so NMI wouldn't correctly preempt HardFault. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1505137930-13255-5-git-send-email-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 1fecfd6..d3e2056 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -152,8 +152,12 @@ static void nvic_recompute_state(NVICState *s) } } =20 + if (active_prio > 0) { + active_prio &=3D nvic_gprio_mask(s); + } + s->vectpending =3D pend_irq; - s->exception_prio =3D active_prio & nvic_gprio_mask(s); + s->exception_prio =3D active_prio; =20 trace_nvic_recompute_state(s->vectpending, s->exception_prio); } @@ -329,7 +333,10 @@ void armv7m_nvic_acknowledge_irq(void *opaque) assert(vec->enabled); assert(vec->pending); =20 - pendgroupprio =3D vec->prio & nvic_gprio_mask(s); + pendgroupprio =3D vec->prio; + if (pendgroupprio > 0) { + pendgroupprio &=3D nvic_gprio_mask(s); + } assert(pendgroupprio < running); =20 trace_nvic_acknowledge_irq(pending, vec->prio); --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150541212220526.861981799717228; Thu, 14 Sep 2017 11:02:02 -0700 (PDT) Received: from localhost ([::1]:49227 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYSf-0002wW-Cb for importer@patchew.org; Thu, 14 Sep 2017 14:02:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46582) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJc-00088D-1q for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJa-00082S-Tt for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:40 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJa-0007vb-Mp for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJQ-0005p0-2T for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:28 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:40 +0100 Message-Id: <1505411573-27848-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 05/18] target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In do_v7m_exception_exit(), there's no need to force the high 4 bits of 'type' to 1 when calling v7m_exception_taken(), because we know that they're always 1 or we could not have got to this "handle return to magic exception return address" code. Remove the unnecessary ORs. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-id: 1505137930-13255-6-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1741e0d..fdd5cc6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6306,7 +6306,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) */ env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - v7m_exception_taken(cpu, type | 0xf0000000); + v7m_exception_taken(cpu, type); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " "stackframe: failed exception return integrity check= \n"); return; @@ -6348,7 +6348,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; v7m_push_stack(cpu); - v7m_exception_taken(cpu, type | 0xf0000000); + v7m_exception_taken(cpu, type); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe= : " "failed exception return integrity check\n"); return; --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505412173284947.6475512676459; Thu, 14 Sep 2017 11:02:53 -0700 (PDT) Received: from localhost ([::1]:49233 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYTU-0005CP-Im for importer@patchew.org; Thu, 14 Sep 2017 14:02:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46563) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJb-00087X-LJ for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJa-00081M-GM for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37368) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJa-0007x0-8U for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJQ-0005pS-O2 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:28 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:41 +0100 Message-Id: <1505411573-27848-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 06/18] target/arm: Add and use defines for EXCRET constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The exception-return magic values get some new bits in v8M, which makes some bit definitions for them worthwhile. We don't use the bit definitions for the switch on the low bits which checks the return type for v7M, because this is defined in the v7M ARM ARM as a set of valid values rather than via per-bit checks. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Message-id: 1505137930-13255-7-git-send-email-peter.maydell@linaro.org --- target/arm/internals.h | 10 ++++++++++ target/arm/helper.c | 14 +++++++++----- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a315354..18be370 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -61,6 +61,16 @@ FIELD(V7M_CONTROL, NPRIV, 0, 1) FIELD(V7M_CONTROL, SPSEL, 1, 1) FIELD(V7M_CONTROL, FPCA, 2, 1) =20 +/* Bit definitions for v7M exception return payload */ +FIELD(V7M_EXCRET, ES, 0, 1) +FIELD(V7M_EXCRET, RES0, 1, 1) +FIELD(V7M_EXCRET, SPSEL, 2, 1) +FIELD(V7M_EXCRET, MODE, 3, 1) +FIELD(V7M_EXCRET, FTYPE, 4, 1) +FIELD(V7M_EXCRET, DCRS, 5, 1) +FIELD(V7M_EXCRET, S, 6, 1) +FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ + /* * For AArch64, map a given EL to an index in the banked_spsr array. * Note that this mapping and the AArch32 mapping defined in bank_number() diff --git a/target/arm/helper.c b/target/arm/helper.c index fdd5cc6..a502e4e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6242,7 +6242,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) " previous exception %d\n", type, env->v7m.exception); =20 - if (extract32(type, 5, 23) !=3D extract32(-1, 5, 23)) { + if ((type & R_V7M_EXCRET_RES1_MASK) !=3D R_V7M_EXCRET_RES1_MASK) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in excep= tion " "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", t= ype); } @@ -6255,7 +6255,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) */ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - int es =3D type & 1; + int es =3D type & R_V7M_EXCRET_ES_MASK; if (armv7m_nvic_raw_execution_priority(env->nvic) >=3D 0) { env->v7m.faultmask[es] =3D 0; } @@ -6491,12 +6491,16 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) return; /* Never happens. Keep compiler happy. */ } =20 - lr =3D 0xfffffff1; + lr =3D R_V7M_EXCRET_RES1_MASK | + R_V7M_EXCRET_S_MASK | + R_V7M_EXCRET_DCRS_MASK | + R_V7M_EXCRET_FTYPE_MASK | + R_V7M_EXCRET_ES_MASK; if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { - lr |=3D 4; + lr |=3D R_V7M_EXCRET_SPSEL_MASK; } if (!arm_v7m_is_handler_mode(env)) { - lr |=3D 8; + lr |=3D R_V7M_EXCRET_MODE_MASK; } =20 v7m_push_stack(cpu); --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150541233484136.54835181816384; Thu, 14 Sep 2017 11:05:34 -0700 (PDT) Received: from localhost ([::1]:49255 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYW3-00086i-S0 for importer@patchew.org; Thu, 14 Sep 2017 14:05:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46571) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJb-00087n-Q0 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJa-00081F-E2 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJa-0007iP-6a for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJR-0005pt-D8 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:29 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:42 +0100 Message-Id: <1505411573-27848-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 07/18] target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 In the v7M and v8M ARM ARM, the magic exception return values are referred to as EXC_RETURN values, and in QEMU we use V7M_EXCRET_* constants to define bits within them. Rename the 'type' variable which holds the exception return value in do_v7m_exception_exit() to excret, making it clearer that it does hold an EXC_RETURN value. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Message-id: 1505137930-13255-8-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a502e4e..4f41841 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6212,7 +6212,7 @@ static void v7m_push_stack(ARMCPU *cpu) static void do_v7m_exception_exit(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; - uint32_t type; + uint32_t excret; uint32_t xpsr; bool ufault =3D false; bool return_to_sp_process =3D false; @@ -6233,18 +6233,19 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * the target value up between env->regs[15] and env->thumb in * gen_bx(). Reconstitute it. */ - type =3D env->regs[15]; + excret =3D env->regs[15]; if (env->thumb) { - type |=3D 1; + excret |=3D 1; } =20 qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32 " previous exception %d\n", - type, env->v7m.exception); + excret, env->v7m.exception); =20 - if ((type & R_V7M_EXCRET_RES1_MASK) !=3D R_V7M_EXCRET_RES1_MASK) { + if ((excret & R_V7M_EXCRET_RES1_MASK) !=3D R_V7M_EXCRET_RES1_MASK) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in excep= tion " - "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", t= ype); + "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", + excret); } =20 if (env->v7m.exception !=3D ARMV7M_EXCP_NMI) { @@ -6255,7 +6256,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) */ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - int es =3D type & R_V7M_EXCRET_ES_MASK; + int es =3D excret & R_V7M_EXCRET_ES_MASK; if (armv7m_nvic_raw_execution_priority(env->nvic) >=3D 0) { env->v7m.faultmask[es] =3D 0; } @@ -6283,7 +6284,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) g_assert_not_reached(); } =20 - switch (type & 0xf) { + switch (excret & 0xf) { case 1: /* Return to Handler */ return_to_handler =3D true; break; @@ -6306,7 +6307,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) */ env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - v7m_exception_taken(cpu, type); + v7m_exception_taken(cpu, excret); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " "stackframe: failed exception return integrity check= \n"); return; @@ -6341,14 +6342,14 @@ static void do_v7m_exception_exit(ARMCPU *cpu) =20 /* The restored xPSR exception field will be zero if we're * resuming in Thread mode. If that doesn't match what the - * exception return type specified then this is a UsageFault. + * exception return excret specified then this is a UsageFault. */ if (return_to_handler !=3D arm_v7m_is_handler_mode(env)) { /* Take an INVPC UsageFault by pushing the stack again. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; v7m_push_stack(cpu); - v7m_exception_taken(cpu, type); + v7m_exception_taken(cpu, excret); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe= : " "failed exception return integrity check\n"); return; --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505412532430988.6683971073829; Thu, 14 Sep 2017 11:08:52 -0700 (PDT) Received: from localhost ([::1]:49271 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYZH-0002a0-Mw for importer@patchew.org; Thu, 14 Sep 2017 14:08:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46542) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJb-000879-8o for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJZ-00080I-V3 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJZ-0007vb-NL for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJS-0005qK-1V for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:30 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:43 +0100 Message-Id: <1505411573-27848-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 08/18] xlnx-ep108: Rename to ZCU102 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Alistair Francis The EP108 is a early access development board. Now that silicon is in production people have access to the ZCU102. Let's rename the internal QEMU files and variables to use the ZCU102. There is no functional change here as the EP108 is still a valid board option. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- hw/arm/Makefile.objs | 2 +- hw/arm/{xlnx-ep108.c =3D> xlnx-zcu102.c} | 30 +++++++++++++++-------------= -- 2 files changed, 16 insertions(+), 16 deletions(-) rename hw/arm/{xlnx-ep108.c =3D> xlnx-zcu102.c} (85%) diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index a2e56ec..5ee6f7d 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -13,7 +13,7 @@ obj-y +=3D omap1.o omap2.o strongarm.o obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboard.o obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o raspi.o obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o -obj-$(CONFIG_XLNX_ZYNQMP) +=3D xlnx-zynqmp.o xlnx-ep108.o +obj-$(CONFIG_XLNX_ZYNQMP) +=3D xlnx-zynqmp.o xlnx-zcu102.o obj-$(CONFIG_FSL_IMX25) +=3D fsl-imx25.o imx25_pdk.o obj-$(CONFIG_FSL_IMX31) +=3D fsl-imx31.o kzm.o obj-$(CONFIG_FSL_IMX6) +=3D fsl-imx6.o sabrelite.o diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-zcu102.c similarity index 85% rename from hw/arm/xlnx-ep108.c rename to hw/arm/xlnx-zcu102.c index c339cd4..e9702ed 100644 --- a/hw/arm/xlnx-ep108.c +++ b/hw/arm/xlnx-zcu102.c @@ -1,5 +1,5 @@ /* - * Xilinx ZynqMP EP108 board + * Xilinx ZynqMP ZCU102 board * * Copyright (C) 2015 Xilinx Inc * Written by Peter Crosthwaite @@ -25,16 +25,16 @@ #include "exec/address-spaces.h" #include "qemu/log.h" =20 -typedef struct XlnxEP108 { +typedef struct XlnxZCU102 { XlnxZynqMPState soc; MemoryRegion ddr_ram; -} XlnxEP108; +} XlnxZCU102; =20 -static struct arm_boot_info xlnx_ep108_binfo; +static struct arm_boot_info xlnx_zcu102_binfo; =20 -static void xlnx_ep108_init(MachineState *machine) +static void xlnx_zcu102_init(MachineState *machine) { - XlnxEP108 *s =3D g_new0(XlnxEP108, 1); + XlnxZCU102 *s =3D g_new0(XlnxZCU102, 1); int i; uint64_t ram_size =3D machine->ram_size; =20 @@ -47,7 +47,7 @@ static void xlnx_ep108_init(MachineState *machine) } =20 if (ram_size < 0x08000000) { - qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for EP108", + qemu_log("WARNING: RAM size 0x%" PRIx64 " is small for ZCU102", ram_size); } =20 @@ -108,18 +108,18 @@ static void xlnx_ep108_init(MachineState *machine) =20 /* TODO create and connect IDE devices for ide_drive_get() */ =20 - xlnx_ep108_binfo.ram_size =3D ram_size; - xlnx_ep108_binfo.kernel_filename =3D machine->kernel_filename; - xlnx_ep108_binfo.kernel_cmdline =3D machine->kernel_cmdline; - xlnx_ep108_binfo.initrd_filename =3D machine->initrd_filename; - xlnx_ep108_binfo.loader_start =3D 0; - arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_ep108_binfo); + xlnx_zcu102_binfo.ram_size =3D ram_size; + xlnx_zcu102_binfo.kernel_filename =3D machine->kernel_filename; + xlnx_zcu102_binfo.kernel_cmdline =3D machine->kernel_cmdline; + xlnx_zcu102_binfo.initrd_filename =3D machine->initrd_filename; + xlnx_zcu102_binfo.loader_start =3D 0; + arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo); } =20 static void xlnx_ep108_machine_init(MachineClass *mc) { mc->desc =3D "Xilinx ZynqMP EP108 board"; - mc->init =3D xlnx_ep108_init; + mc->init =3D xlnx_zcu102_init; mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; mc->ignore_memory_transaction_failures =3D true; @@ -130,7 +130,7 @@ DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init) static void xlnx_zcu102_machine_init(MachineClass *mc) { mc->desc =3D "Xilinx ZynqMP ZCU102 board"; - mc->init =3D xlnx_ep108_init; + mc->init =3D xlnx_zcu102_init; mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; mc->ignore_memory_transaction_failures =3D true; --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505412406639295.1724601728263; Thu, 14 Sep 2017 11:06:46 -0700 (PDT) Received: from localhost ([::1]:49266 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYXF-00010k-VN for importer@patchew.org; Thu, 14 Sep 2017 14:06:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46510) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJa-00086a-K4 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJZ-0007ze-IG for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37368) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJZ-0007x0-8z for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJS-0005ql-N3 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:30 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:44 +0100 Message-Id: <1505411573-27848-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 09/18] xlnx-zcu102: Manually create the machines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Alistair Francis In preperation for future work let's manually create the Xilnx machines. This will allow us to set properties for the machines in the future. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++-= ---- 1 file changed, 67 insertions(+), 7 deletions(-) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index e9702ed..5b1f184 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -26,15 +26,24 @@ #include "qemu/log.h" =20 typedef struct XlnxZCU102 { + MachineState parent_obj; + XlnxZynqMPState soc; MemoryRegion ddr_ram; } XlnxZCU102; =20 +#define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") +#define ZCU102_MACHINE(obj) \ + OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE) + +#define TYPE_EP108_MACHINE MACHINE_TYPE_NAME("xlnx-ep108") +#define EP108_MACHINE(obj) \ + OBJECT_CHECK(XlnxZCU102, (obj), TYPE_EP108_MACHINE) + static struct arm_boot_info xlnx_zcu102_binfo; =20 -static void xlnx_zcu102_init(MachineState *machine) +static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) { - XlnxZCU102 *s =3D g_new0(XlnxZCU102, 1); int i; uint64_t ram_size =3D machine->ram_size; =20 @@ -116,19 +125,56 @@ static void xlnx_zcu102_init(MachineState *machine) arm_load_kernel(s->soc.boot_cpu_ptr, &xlnx_zcu102_binfo); } =20 -static void xlnx_ep108_machine_init(MachineClass *mc) +static void xlnx_ep108_init(MachineState *machine) +{ + XlnxZCU102 *s =3D EP108_MACHINE(machine); + + xlnx_zynqmp_init(s, machine); +} + +static void xlnx_ep108_machine_instance_init(Object *obj) { +} + +static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + mc->desc =3D "Xilinx ZynqMP EP108 board"; - mc->init =3D xlnx_zcu102_init; + mc->init =3D xlnx_ep108_init; mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; mc->ignore_memory_transaction_failures =3D true; } =20 -DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init) +static const TypeInfo xlnx_ep108_machine_init_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("xlnx-ep108"), + .parent =3D TYPE_MACHINE, + .class_init =3D xlnx_ep108_machine_class_init, + .instance_init =3D xlnx_ep108_machine_instance_init, + .instance_size =3D sizeof(XlnxZCU102), +}; =20 -static void xlnx_zcu102_machine_init(MachineClass *mc) +static void xlnx_ep108_machine_init_register_types(void) { + type_register_static(&xlnx_ep108_machine_init_typeinfo); +} + +static void xlnx_zcu102_init(MachineState *machine) +{ + XlnxZCU102 *s =3D ZCU102_MACHINE(machine); + + xlnx_zynqmp_init(s, machine); +} + +static void xlnx_zcu102_machine_instance_init(Object *obj) +{ +} + +static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + mc->desc =3D "Xilinx ZynqMP ZCU102 board"; mc->init =3D xlnx_zcu102_init; mc->block_default_type =3D IF_IDE; @@ -136,4 +182,18 @@ static void xlnx_zcu102_machine_init(MachineClass *mc) mc->ignore_memory_transaction_failures =3D true; } =20 -DEFINE_MACHINE("xlnx-zcu102", xlnx_zcu102_machine_init) +static const TypeInfo xlnx_zcu102_machine_init_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("xlnx-zcu102"), + .parent =3D TYPE_MACHINE, + .class_init =3D xlnx_zcu102_machine_class_init, + .instance_init =3D xlnx_zcu102_machine_instance_init, + .instance_size =3D sizeof(XlnxZCU102), +}; + +static void xlnx_zcu102_machine_init_register_types(void) +{ + type_register_static(&xlnx_zcu102_machine_init_typeinfo); +} + +type_init(xlnx_zcu102_machine_init_register_types) +type_init(xlnx_ep108_machine_init_register_types) --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505412281945593.7382751050277; Thu, 14 Sep 2017 11:04:41 -0700 (PDT) Received: from localhost ([::1]:49248 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYVF-0007L1-7s for importer@patchew.org; Thu, 14 Sep 2017 14:04:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46488) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJa-00085o-1A for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJZ-0007yS-0O for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJY-0007vb-Pf for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:36 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJT-0005rC-Aj for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:31 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:45 +0100 Message-Id: <1505411573-27848-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 10/18] xlnx-zcu102: Add a machine level secure property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Add a machine level secure property. This defaults to false and can be set to true using this machine command line argument: -machine xlnx-zcu102,secure=3Don This follows what the ARM virt machine does. This property only applies to the ZCU102 machine. The EP108 machine does not have this property. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 5b1f184..bd573c4 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -30,6 +30,8 @@ typedef struct XlnxZCU102 { =20 XlnxZynqMPState soc; MemoryRegion ddr_ram; + + bool secure; } XlnxZCU102; =20 #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") @@ -42,6 +44,20 @@ typedef struct XlnxZCU102 { =20 static struct arm_boot_info xlnx_zcu102_binfo; =20 +static bool zcu102_get_secure(Object *obj, Error **errp) +{ + XlnxZCU102 *s =3D ZCU102_MACHINE(obj); + + return s->secure; +} + +static void zcu102_set_secure(Object *obj, bool value, Error **errp) +{ + XlnxZCU102 *s =3D ZCU102_MACHINE(obj); + + s->secure =3D value; +} + static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) { int i; @@ -69,6 +85,8 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState = *machine) =20 object_property_set_link(OBJECT(&s->soc), OBJECT(&s->ddr_ram), "ddr-ram", &error_abort); + object_property_set_bool(OBJECT(&s->soc), s->secure, "secure", + &error_fatal); =20 object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fat= al); =20 @@ -134,6 +152,10 @@ static void xlnx_ep108_init(MachineState *machine) =20 static void xlnx_ep108_machine_instance_init(Object *obj) { + XlnxZCU102 *s =3D EP108_MACHINE(obj); + + /* EP108, we don't support setting secure */ + s->secure =3D false; } =20 static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) @@ -169,6 +191,16 @@ static void xlnx_zcu102_init(MachineState *machine) =20 static void xlnx_zcu102_machine_instance_init(Object *obj) { + XlnxZCU102 *s =3D ZCU102_MACHINE(obj); + + /* Default to secure mode being disabled */ + s->secure =3D false; + object_property_add_bool(obj, "secure", zcu102_get_secure, + zcu102_set_secure, NULL); + object_property_set_description(obj, "secure", + "Set on/off to enable/disable the ARM " + "Security Extensions (TrustZone)", + NULL); } =20 static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505411686239583.1276800035648; Thu, 14 Sep 2017 10:54:46 -0700 (PDT) Received: from localhost ([::1]:49184 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYLd-0001B4-HS for importer@patchew.org; Thu, 14 Sep 2017 13:54:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46476) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJZ-00085b-OF for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJY-0007xk-Fz for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJY-0007iP-7e for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:36 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJT-0005rd-Vp for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:31 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:46 +0100 Message-Id: <1505411573-27848-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/18] xlnx-zcu102: Add a machine level virtualization property X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Add a machine level virtualization property. This defaults to false and can= be set to true using this machine command line argument: -machine xlnx-zcu102,virtualization=3Don This follows what the ARM virt machine does. This property only applies to the ZCU102 machine. The EP108 machine does not have this property. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 2 ++ hw/arm/xlnx-zcu102.c | 30 +++++++++++++++++++++++++++++- hw/arm/xlnx-zynqmp.c | 3 ++- 3 files changed, 33 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index c2931bf..6eff81a 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -91,6 +91,8 @@ typedef struct XlnxZynqMPState { =20 /* Has the ARM Security extensions? */ bool secure; + /* Has the ARM Virtualization extensions? */ + bool virt; /* Has the RPU subsystem? */ bool has_rpu; } XlnxZynqMPState; diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index bd573c4..42deefd 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -32,6 +32,7 @@ typedef struct XlnxZCU102 { MemoryRegion ddr_ram; =20 bool secure; + bool virt; } XlnxZCU102; =20 #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") @@ -58,6 +59,20 @@ static void zcu102_set_secure(Object *obj, bool value, E= rror **errp) s->secure =3D value; } =20 +static bool zcu102_get_virt(Object *obj, Error **errp) +{ + XlnxZCU102 *s =3D ZCU102_MACHINE(obj); + + return s->virt; +} + +static void zcu102_set_virt(Object *obj, bool value, Error **errp) +{ + XlnxZCU102 *s =3D ZCU102_MACHINE(obj); + + s->virt =3D value; +} + static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState *machine) { int i; @@ -87,6 +102,8 @@ static void xlnx_zynqmp_init(XlnxZCU102 *s, MachineState= *machine) "ddr-ram", &error_abort); object_property_set_bool(OBJECT(&s->soc), s->secure, "secure", &error_fatal); + object_property_set_bool(OBJECT(&s->soc), s->virt, "virtualization", + &error_fatal); =20 object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fat= al); =20 @@ -154,8 +171,9 @@ static void xlnx_ep108_machine_instance_init(Object *ob= j) { XlnxZCU102 *s =3D EP108_MACHINE(obj); =20 - /* EP108, we don't support setting secure */ + /* EP108, we don't support setting secure or virt */ s->secure =3D false; + s->virt =3D false; } =20 static void xlnx_ep108_machine_class_init(ObjectClass *oc, void *data) @@ -201,6 +219,16 @@ static void xlnx_zcu102_machine_instance_init(Object *= obj) "Set on/off to enable/disable the ARM " "Security Extensions (TrustZone)", NULL); + + /* Default to virt (EL2) being disabled */ + s->virt =3D false; + object_property_add_bool(obj, "virtualization", zcu102_get_virt, + zcu102_set_virt, NULL); + object_property_set_description(obj, "virtualization", + "Set on/off to enable/disable emulatin= g a " + "guest CPU which implements the ARM " + "Virtualization Extensions", + NULL); } =20 static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 22c2a33..2b27daf 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -255,7 +255,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) object_property_set_bool(OBJECT(&s->apu_cpu[i]), s->secure, "has_el3", NULL); object_property_set_bool(OBJECT(&s->apu_cpu[i]), - false, "has_el2", NULL); + s->virt, "has_el2", NULL); object_property_set_int(OBJECT(&s->apu_cpu[i]), GIC_BASE_ADDR, "reset-cbar", &error_abort); object_property_set_bool(OBJECT(&s->apu_cpu[i]), true, "realized", @@ -427,6 +427,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) static Property xlnx_zynqmp_props[] =3D { DEFINE_PROP_STRING("boot-cpu", XlnxZynqMPState, boot_cpu), DEFINE_PROP_BOOL("secure", XlnxZynqMPState, secure, false), + DEFINE_PROP_BOOL("virtualization", XlnxZynqMPState, virt, false), DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGI= ON, MemoryRegion *), --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505411848306413.89290061990994; Thu, 14 Sep 2017 10:57:28 -0700 (PDT) Received: from localhost ([::1]:49197 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYOF-0004Zc-IB for importer@patchew.org; Thu, 14 Sep 2017 13:57:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46431) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJY-00084n-DN for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJX-0007wf-Hh for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:36 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJX-0007iP-AR for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:35 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJU-0005s4-LL for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:32 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:47 +0100 Message-Id: <1505411573-27848-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 12/18] xlnx-zcu102: Mark the EP108 machine as deprecated X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Alistair Francis The EP108 is the same as the ZCU102, mark it as deprecated as we don't need two machines. Signed-off-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 42deefd..519a16e 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -180,7 +180,7 @@ static void xlnx_ep108_machine_class_init(ObjectClass *= oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); =20 - mc->desc =3D "Xilinx ZynqMP EP108 board"; + mc->desc =3D "Xilinx ZynqMP EP108 board (Deprecated, please use xlnx-z= cu102)"; mc->init =3D xlnx_ep108_init; mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505411683525341.51420182376626; Thu, 14 Sep 2017 10:54:43 -0700 (PDT) Received: from localhost ([::1]:49183 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYLY-000176-TN for importer@patchew.org; Thu, 14 Sep 2017 13:54:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46413) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJX-00084g-PU for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJW-0007vm-Ib for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:35 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJW-0007iP-Bb for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:34 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJV-0005sV-9U for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:48 +0100 Message-Id: <1505411573-27848-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/18] AArch64: Fix single stepping of ERET instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Jaroslaw Pelczar Previously when single stepping through ERET instruction via GDB would result in debugger entering the "next" PC after ERET instruction. When debugging in kernel mode, this will also cause unintended behavior, because debugger will try to access memory from EL0 point of view. Signed-off-by: Jaroslaw Pelczar Message-id: 001c01d32895$483027f0$d89077d0$@samsung.com Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9017e30..1bc12d9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11348,6 +11348,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) default: gen_a64_set_pc_im(dc->pc); /* fall through */ + case DISAS_EXIT: case DISAS_JUMP: if (dc->base.singlestep_enabled) { gen_exception_internal(EXCP_DEBUG); --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505411983016871.3904469986321; Thu, 14 Sep 2017 10:59:43 -0700 (PDT) Received: from localhost ([::1]:49206 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYQQ-0007Lu-3q for importer@patchew.org; Thu, 14 Sep 2017 13:59:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46423) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJY-00084m-6B for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJX-0007wN-6n for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:36 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJW-0007vb-Vd for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:35 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJV-0005t0-U7 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:49 +0100 Message-Id: <1505411573-27848-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 14/18] target/arm: Avoid an extra temporary for store_exclusive X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Instead of copying addr to a local temp, reuse the value (which we have just compared as equal) already saved in cpu_exclusive_addr. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-id: 20170908163859.29820-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 26 +++++++++----------------- 1 file changed, 9 insertions(+), 17 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1bc12d9..083568c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1894,7 +1894,7 @@ static void gen_load_exclusive(DisasContext *s, int r= t, int rt2, } =20 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, - TCGv_i64 inaddr, int size, int is_pair) + TCGv_i64 addr, int size, int is_pair) { /* if (env->exclusive_addr =3D=3D addr && env->exclusive_val =3D=3D [a= ddr] * && (!is_pair || env->exclusive_high =3D=3D [addr + datasize])) { @@ -1910,13 +1910,8 @@ static void gen_store_exclusive(DisasContext *s, int= rd, int rt, int rt2, */ TCGLabel *fail_label =3D gen_new_label(); TCGLabel *done_label =3D gen_new_label(); - TCGv_i64 addr =3D tcg_temp_local_new_i64(); TCGv_i64 tmp; =20 - /* Copy input into a local temp so it is not trashed when the - * basic block ends at the branch insn. - */ - tcg_gen_mov_i64(addr, inaddr); tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); =20 tmp =3D tcg_temp_new_i64(); @@ -1927,27 +1922,24 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, } else { tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); } - tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, tmp, + tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, + cpu_exclusive_val, tmp, get_mem_index(s), MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } else if (s->be_data =3D=3D MO_LE) { - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, = rt), - cpu_reg(s, rt2)); + gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_add= r, + cpu_reg(s, rt), cpu_reg(s, rt2)= ); } else { - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, cpu_reg(s, = rt), - cpu_reg(s, rt2)); + gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_add= r, + cpu_reg(s, rt), cpu_reg(s, rt2)= ); } } else { - TCGv_i64 val =3D cpu_reg(s, rt); - tcg_gen_atomic_cmpxchg_i64(tmp, addr, cpu_exclusive_val, val, - get_mem_index(s), + tcg_gen_atomic_cmpxchg_i64(tmp, cpu_exclusive_addr, cpu_exclusive_= val, + cpu_reg(s, rt), get_mem_index(s), size | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); } - - tcg_temp_free_i64(addr); - tcg_gen_mov_i64(cpu_reg(s, rd), tmp); tcg_temp_free_i64(tmp); tcg_gen_br(done_label); --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150541184563355.7916613078952; Thu, 14 Sep 2017 10:57:25 -0700 (PDT) Received: from localhost ([::1]:49196 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYOC-0004Wj-SB for importer@patchew.org; Thu, 14 Sep 2017 13:57:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46452) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJY-00084s-W0 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJY-0007xK-35 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJX-0007vb-Sc for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:36 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJW-0005tE-JJ for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:34 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:50 +0100 Message-Id: <1505411573-27848-16-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 15/18] hw/pci-host/gpex: Set INTx index/gsi mapping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Pranavkumar Sawargaonkar To implement INTx to gsi routing we need to pass the gpex host bridge the gsi associated to each INTx index. Let's introduce irq_num array and gpex_set_irq_num setter function. Signed-off-by: Pranavkumar Sawargaonkar Signed-off-by: Tushar Jagad Signed-off-by: Eric Auger Tested-by: Feng Kan Reviewed-by: Andrew Jones Message-id: 1505296004-6798-2-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell --- include/hw/pci-host/gpex.h | 3 +++ hw/pci-host/gpex.c | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index 68c9348..aef38b8 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -51,6 +51,9 @@ typedef struct GPEXHost { MemoryRegion io_ioport; MemoryRegion io_mmio; qemu_irq irq[GPEX_NUM_IRQS]; + int irq_num[GPEX_NUM_IRQS]; } GPEXHost; =20 +int gpex_set_irq_num(GPEXHost *s, int index, int gsi); + #endif /* HW_GPEX_H */ diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index 83084b9..41a884d 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -43,6 +43,16 @@ static void gpex_set_irq(void *opaque, int irq_num, int = level) qemu_set_irq(s->irq[irq_num], level); } =20 +int gpex_set_irq_num(GPEXHost *s, int index, int gsi) +{ + if (index >=3D GPEX_NUM_IRQS) { + return -EINVAL; + } + + s->irq_num[index] =3D gsi; + return 0; +} + static void gpex_host_realize(DeviceState *dev, Error **errp) { PCIHostState *pci =3D PCI_HOST_BRIDGE(dev); --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505412116155221.21748321597022; Thu, 14 Sep 2017 11:01:56 -0700 (PDT) Received: from localhost ([::1]:49225 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYSZ-0002pI-Co for importer@patchew.org; Thu, 14 Sep 2017 14:01:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46460) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJZ-000854-8p for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJY-0007xy-HX for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37368) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJY-0007x0-As for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:36 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJX-0005th-9k for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:35 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:51 +0100 Message-Id: <1505411573-27848-17-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/18] hw/arm/virt: Set INTx/gsi mapping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Pranavkumar Sawargaonkar Let's provide the GPEX host bridge with the INTx/gsi mapping. This is needed for INTx/gsi routing. Signed-off-by: Pranavkumar Sawargaonkar Signed-off-by: Tushar Jagad Signed-off-by: Eric Auger Reviewed-by: Andrew Jones Tested-by: Feng Kan Message-id: 1505296004-6798-3-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index fe96557..cfd834d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1057,6 +1057,7 @@ static void create_pcie(const VirtMachineState *vms, = qemu_irq *pic) =20 for (i =3D 0; i < GPEX_NUM_IRQS; i++) { sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]); + gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); } =20 pci =3D PCI_HOST_BRIDGE(dev); --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505411691990892.2380995969577; Thu, 14 Sep 2017 10:54:51 -0700 (PDT) Received: from localhost ([::1]:49185 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYLj-0001Jj-79 for importer@patchew.org; Thu, 14 Sep 2017 13:54:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46500) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJa-00086G-CE for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJZ-0007zX-GQ for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37364) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJZ-0007iP-8g for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJX-0005u1-UM for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:35 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:52 +0100 Message-Id: <1505411573-27848-18-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 17/18] hw/pci-host/gpex: Implement PCI INTx routing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Pranavkumar Sawargaonkar Now we are able to retrieve the gsi from the INTx pin, let's enable intx_to_irq routing. From that point on, irqfd becomes usable along with INTx when assigning a PCIe device. Signed-off-by: Pranavkumar Sawargaonkar Signed-off-by: Tushar Jagad Signed-off-by: Eric Auger Reviewed-by: Andrew Jones Tested-by: Feng Kan Message-id: 1505296004-6798-4-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell --- hw/pci-host/gpex.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index 41a884d..be25245 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -53,6 +53,17 @@ int gpex_set_irq_num(GPEXHost *s, int index, int gsi) return 0; } =20 +static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin) +{ + PCIINTxRoute route; + GPEXHost *s =3D opaque; + + route.mode =3D PCI_INTX_ENABLED; + route.irq =3D s->irq_num[pin]; + + return route; +} + static void gpex_host_realize(DeviceState *dev, Error **errp) { PCIHostState *pci =3D PCI_HOST_BRIDGE(dev); @@ -77,6 +88,7 @@ static void gpex_host_realize(DeviceState *dev, Error **e= rrp) &s->io_ioport, 0, 4, TYPE_PCIE_BUS); =20 qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus)); + pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq); qdev_init_nofail(DEVICE(&s->gpex_root)); } =20 --=20 2.7.4 From nobody Sun May 5 05:15:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505412028765327.6946687832876; Thu, 14 Sep 2017 11:00:28 -0700 (PDT) Received: from localhost ([::1]:49211 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYRA-0000IC-1c for importer@patchew.org; Thu, 14 Sep 2017 14:00:28 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46523) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dsYJa-00086k-QL for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dsYJZ-00080Q-VS for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:38 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37370) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dsYJZ-0007yZ-Nm for qemu-devel@nongnu.org; Thu, 14 Sep 2017 13:52:37 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dsYJY-0005uU-J4 for qemu-devel@nongnu.org; Thu, 14 Sep 2017 18:52:36 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 14 Sep 2017 18:52:53 +0100 Message-Id: <1505411573-27848-19-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> References: <1505411573-27848-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 18/18] mps2-an511: Fix wiring of UART overflow interrupt lines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Fix an error that meant we were wiring every UART's overflow interrupts into the same inputs 0 and 1 of the OR gate, rather than giving each its own input. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 1505232834-20890-1-git-send-email-peter.maydell@linaro.org --- hw/arm/mps2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index abb0ab6..769cff8 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -287,8 +287,8 @@ static void mps2_common_init(MachineState *machine) cmsdk_apb_uart_create(uartbase[i], qdev_get_gpio_in(txrx_orgate_dev, 0), qdev_get_gpio_in(txrx_orgate_dev, 1), - qdev_get_gpio_in(orgate_dev, 0), - qdev_get_gpio_in(orgate_dev, 1), + qdev_get_gpio_in(orgate_dev, i * 2), + qdev_get_gpio_in(orgate_dev, i * 2 + 1), NULL, uartchr, SYSCLK_FRQ); } --=20 2.7.4