From nobody Tue Nov 4 06:40:47 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505241000541933.188148099449; Tue, 12 Sep 2017 11:30:00 -0700 (PDT) Received: from localhost ([::1]:38029 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drpwd-0002Wf-G4 for importer@patchew.org; Tue, 12 Sep 2017 14:29:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43576) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drph6-0003X3-5f for qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1drph4-0006UU-JY for qemu-devel@nongnu.org; Tue, 12 Sep 2017 14:13:56 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37316) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1drph1-0006QF-4q; Tue, 12 Sep 2017 14:13:51 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drpgy-00018i-Ao; Tue, 12 Sep 2017 19:13:48 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 12 Sep 2017 19:14:00 +0100 Message-Id: <1505240046-11454-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> References: <1505240046-11454-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 13/19] nvic: Implement v8M changes to fixed priority exceptions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In v7M, the fixed-priority exceptions are: Reset: -3 NMI: -2 HardFault: -1 In v8M, this changes because Secure HardFault may need to be prioritised above NMI: Reset: -4 Secure HardFault if AIRCR.BFHFNMINS =3D=3D 1: -3 NMI: -2 Secure HardFault if AIRCR.BFHFNMINS =3D=3D 0: -1 NonSecure HardFault: -1 Make these changes, including support for changing the priority of Secure HardFault as AIRCR.BFHFNMINS changes. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/armv7m_nvic.c | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index c4670f7..db2f170 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -937,6 +937,12 @@ static void nvic_writel(NVICState *s, uint32_t offset,= uint32_t value, (R_V7M_AIRCR_SYSRESETREQS_MASK | R_V7M_AIRCR_BFHFNMINS_MASK | R_V7M_AIRCR_PRIS_MASK); + /* BFHFNMINS changes the priority of Secure HardFault */ + if (cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { + s->sec_vectors[ARMV7M_EXCP_HARD].prio =3D -3; + } else { + s->sec_vectors[ARMV7M_EXCP_HARD].prio =3D -1; + } } nvic_irq_update(s); } @@ -1452,9 +1458,12 @@ static int nvic_post_load(void *opaque, int version_= id) { NVICState *s =3D opaque; unsigned i; + int resetprio; =20 /* Check for out of range priority settings */ - if (s->vectors[ARMV7M_EXCP_RESET].prio !=3D -3 || + resetprio =3D arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3; + + if (s->vectors[ARMV7M_EXCP_RESET].prio !=3D resetprio || s->vectors[ARMV7M_EXCP_NMI].prio !=3D -2 || s->vectors[ARMV7M_EXCP_HARD].prio !=3D -1) { return 1; @@ -1497,7 +1506,12 @@ static int nvic_security_post_load(void *opaque, int= version_id) int i; =20 /* Check for out of range priority settings */ - if (s->sec_vectors[ARMV7M_EXCP_HARD].prio !=3D -1) { + if (s->sec_vectors[ARMV7M_EXCP_HARD].prio !=3D -1 + && s->sec_vectors[ARMV7M_EXCP_HARD].prio !=3D -3) { + /* We can't cross-check against AIRCR.BFHFNMINS as we don't know + * if the CPU state has been migrated yet; a mismatch won't + * cause the emulation to blow up, though. + */ return 1; } for (i =3D ARMV7M_EXCP_MEM; i < ARRAY_SIZE(s->sec_vectors); i++) { @@ -1544,6 +1558,7 @@ static Property props_nvic[] =3D { =20 static void armv7m_nvic_reset(DeviceState *dev) { + int resetprio; NVICState *s =3D NVIC(dev); =20 s->vectors[ARMV7M_EXCP_NMI].enabled =3D 1; @@ -1556,7 +1571,8 @@ static void armv7m_nvic_reset(DeviceState *dev) s->vectors[ARMV7M_EXCP_PENDSV].enabled =3D 1; s->vectors[ARMV7M_EXCP_SYSTICK].enabled =3D 1; =20 - s->vectors[ARMV7M_EXCP_RESET].prio =3D -3; + resetprio =3D arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3; + s->vectors[ARMV7M_EXCP_RESET].prio =3D resetprio; s->vectors[ARMV7M_EXCP_NMI].prio =3D -2; s->vectors[ARMV7M_EXCP_HARD].prio =3D -1; =20 --=20 2.7.4