From nobody Mon Apr 29 01:23:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505138206685848.6421176054979; Mon, 11 Sep 2017 06:56:46 -0700 (PDT) Received: from localhost ([::1]:57930 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drPCf-0005nX-NW for importer@patchew.org; Mon, 11 Sep 2017 09:56:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41828) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drP8H-0001qi-2h for qemu-devel@nongnu.org; Mon, 11 Sep 2017 09:52:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1drP8D-0002Ih-1L for qemu-devel@nongnu.org; Mon, 11 Sep 2017 09:52:13 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1drP84-00023m-RC; Mon, 11 Sep 2017 09:52:01 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7p-0007lo-Gn; Mon, 11 Sep 2017 14:51:45 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 11 Sep 2017 14:52:04 +0100 Message-Id: <1505137930-13255-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 1/7] target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Use a symbolic constant M_REG_NUM_BANKS for the array size for registers which are banked by M profile security state, rather than hardcoding lots of 2s. Suggested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- Philippe suggested this in review on the last round of patches but I forgot about it :-( --- target/arm/cpu.h | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 98b9b26..5a1f957 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -81,8 +81,11 @@ * accessed via env->registerfield[env->v7m.secure] (whether the security * extension is implemented or not). */ -#define M_REG_NS 0 -#define M_REG_S 1 +enum { + M_REG_NS =3D 0, + M_REG_S =3D 1, + M_REG_NUM_BANKS =3D 2, +}; =20 /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 @@ -433,19 +436,19 @@ typedef struct CPUARMState { uint32_t other_sp; uint32_t other_ss_msp; uint32_t other_ss_psp; - uint32_t vecbase[2]; - uint32_t basepri[2]; - uint32_t control[2]; - uint32_t ccr[2]; /* Configuration and Control */ - uint32_t cfsr[2]; /* Configurable Fault Status */ + uint32_t vecbase[M_REG_NUM_BANKS]; + uint32_t basepri[M_REG_NUM_BANKS]; + uint32_t control[M_REG_NUM_BANKS]; + uint32_t ccr[M_REG_NUM_BANKS]; /* Configuration and Control */ + uint32_t cfsr[M_REG_NUM_BANKS]; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ - uint32_t mmfar[2]; /* MemManage Fault Address */ + uint32_t mmfar[M_REG_NUM_BANKS]; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ - unsigned mpu_ctrl[2]; /* MPU_CTRL */ + unsigned mpu_ctrl[M_REG_NUM_BANKS]; /* MPU_CTRL */ int exception; - uint32_t primask[2]; - uint32_t faultmask[2]; + uint32_t primask[M_REG_NUM_BANKS]; + uint32_t faultmask[M_REG_NUM_BANKS]; uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; =20 @@ -546,7 +549,7 @@ typedef struct CPUARMState { uint32_t *drbar; uint32_t *drsr; uint32_t *dracr; - uint32_t rnr[2]; + uint32_t rnr[M_REG_NUM_BANKS]; } pmsav7; =20 /* PMSAv8 MPU */ @@ -556,10 +559,10 @@ typedef struct CPUARMState { * pmsav7.rnr (region number register) * pmsav7_dregion (number of configured regions) */ - uint32_t *rbar[2]; - uint32_t *rlar[2]; - uint32_t mair0[2]; - uint32_t mair1[2]; + uint32_t *rbar[M_REG_NUM_BANKS]; + uint32_t *rlar[M_REG_NUM_BANKS]; + uint32_t mair0[M_REG_NUM_BANKS]; + uint32_t mair1[M_REG_NUM_BANKS]; } pmsav8; =20 void *nvic; --=20 2.7.4 From nobody Mon Apr 29 01:23:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150513805028243.17201650305822; Mon, 11 Sep 2017 06:54:10 -0700 (PDT) Received: from localhost ([::1]:57909 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drPA8-0003M1-Ey for importer@patchew.org; Mon, 11 Sep 2017 09:54:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41726) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drP87-0001gn-6l for qemu-devel@nongnu.org; Mon, 11 Sep 2017 09:52:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1drP86-0002Dl-9d for qemu-devel@nongnu.org; Mon, 11 Sep 2017 09:52:03 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1drP83-00023m-SN; Mon, 11 Sep 2017 09:52:00 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7q-0007m1-6B; Mon, 11 Sep 2017 14:51:46 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 11 Sep 2017 14:52:05 +0100 Message-Id: <1505137930-13255-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 2/7] target/arm: Clear exclusive monitor on v7M reset, exception entry/exit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For M profile we must clear the exclusive monitor on reset, exception entry and exception exit. We weren't doing any of these things; fix this bug. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/arm/internals.h | 10 ++++++++++ target/arm/cpu.c | 6 ++++++ target/arm/helper.c | 2 ++ target/arm/op_helper.c | 2 +- 4 files changed, 19 insertions(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 5d7f24c..a315354 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -444,6 +444,16 @@ void arm_handle_psci_call(ARMCPU *cpu); #endif =20 /** + * arm_clear_exclusive: clear the exclusive monitor + * @env: CPU env + * Clear the CPU's exclusive monitor, like the guest CLREX instruction. + */ +static inline void arm_clear_exclusive(CPUARMState *env) +{ + env->exclusive_addr =3D -1; +} + +/** * ARMMMUFaultInfo: Information describing an ARM MMU Fault * @s2addr: Address that caused a fault at stage 2 * @stage2: True if we faulted at stage 2 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a1acce3..412e94c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -235,6 +235,12 @@ static void arm_cpu_reset(CPUState *s) env->regs[15] =3D 0xFFFF0000; } =20 + /* M profile requires that reset clears the exclusive monitor; + * A profile does not, but clearing it makes more sense than having it + * set with an exclusive access on address zero. + */ + arm_clear_exclusive(env); + env->vfp.xregs[ARM_VFP_FPEXC] =3D 0; #endif =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 329e517..668e367 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6175,6 +6175,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t= lr) =20 armv7m_nvic_acknowledge_irq(env->nvic); switch_v7m_sp(env, 0); + arm_clear_exclusive(env); /* Clear IT bits */ env->condexec_bits =3D 0; env->regs[14] =3D lr; @@ -6354,6 +6355,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } =20 /* Otherwise, we have a successful exception exit. */ + arm_clear_exclusive(env); qemu_log_mask(CPU_LOG_INT, "...successful exception return\n"); } =20 diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index d1bca46..6a60464 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -1022,7 +1022,7 @@ void HELPER(exception_return)(CPUARMState *env) =20 aarch64_save_sp(env, cur_el); =20 - env->exclusive_addr =3D -1; + arm_clear_exclusive(env); =20 /* We must squash the PSTATE.SS bit to zero unless both of the * following hold: --=20 2.7.4 From nobody Mon Apr 29 01:23:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150513804336453.130123721237965; Mon, 11 Sep 2017 06:54:03 -0700 (PDT) Received: from localhost ([::1]:57908 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drPA2-0003GU-6C for importer@patchew.org; Mon, 11 Sep 2017 09:54:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41683) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drP85-0001f9-R9 for qemu-devel@nongnu.org; Mon, 11 Sep 2017 09:52:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1drP85-0002Cc-05 for qemu-devel@nongnu.org; Mon, 11 Sep 2017 09:52:01 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1drP82-00023m-UK; Mon, 11 Sep 2017 09:51:59 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7q-0007mE-Rl; Mon, 11 Sep 2017 14:51:46 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 11 Sep 2017 14:52:06 +0100 Message-Id: <1505137930-13255-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 3/7] target/arm: Get PRECISERR and IBUSERR the right way round X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For a bus fault, the M profile BFSR bit PRECISERR means a bus fault on a data access, and IBUSERR means a bus fault on an instruction access. We had these the wrong way around; fix this. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 668e367..1741e0d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6430,15 +6430,15 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) case 0x8: /* External Abort */ switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: - env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_PRECISERR_MASK; - qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n"); + env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_IBUSERR_MASK; + qemu_log_mask(CPU_LOG_INT, "...with CFSR.IBUSERR\n"); break; case EXCP_DATA_ABORT: env->v7m.cfsr[M_REG_NS] |=3D - (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK); + (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK= ); env->v7m.bfar =3D env->exception.vaddress; qemu_log_mask(CPU_LOG_INT, - "...with CFSR.IBUSERR and BFAR 0x%x\n", + "...with CFSR.PRECISERR and BFAR 0x%x\n", env->v7m.bfar); break; } --=20 2.7.4 From nobody Mon Apr 29 01:23:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505138051172719.2470477437683; Mon, 11 Sep 2017 06:54:11 -0700 (PDT) Received: from localhost ([::1]:57910 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drPAA-0003NN-BO for importer@patchew.org; Mon, 11 Sep 2017 09:54:10 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41632) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drP83-0001cu-02 for qemu-devel@nongnu.org; Mon, 11 Sep 2017 09:52:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1drP82-0002AW-7K for qemu-devel@nongnu.org; Mon, 11 Sep 2017 09:51:59 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1drP80-00023m-2W; Mon, 11 Sep 2017 09:51:56 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7r-0007mR-ID; Mon, 11 Sep 2017 14:51:47 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 11 Sep 2017 14:52:07 +0100 Message-Id: <1505137930-13255-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 4/7] nvic: Don't apply group priority mask to negative priorities X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In several places we were unconditionally applying the nvic_gprio_mask() to a priority value. This is incorrect if the priority is one of the fixed negative priority values (for NMI and HardFault), so don't do it. This bug would have caused both NMI and HardFault to be considered as the same priority and so NMI wouldn't correctly preempt HardFault. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/armv7m_nvic.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 1fecfd6..d3e2056 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -152,8 +152,12 @@ static void nvic_recompute_state(NVICState *s) } } =20 + if (active_prio > 0) { + active_prio &=3D nvic_gprio_mask(s); + } + s->vectpending =3D pend_irq; - s->exception_prio =3D active_prio & nvic_gprio_mask(s); + s->exception_prio =3D active_prio; =20 trace_nvic_recompute_state(s->vectpending, s->exception_prio); } @@ -329,7 +333,10 @@ void armv7m_nvic_acknowledge_irq(void *opaque) assert(vec->enabled); assert(vec->pending); =20 - pendgroupprio =3D vec->prio & nvic_gprio_mask(s); + pendgroupprio =3D vec->prio; + if (pendgroupprio > 0) { + pendgroupprio &=3D nvic_gprio_mask(s); + } assert(pendgroupprio < running); =20 trace_nvic_acknowledge_irq(pending, vec->prio); --=20 2.7.4 From nobody Mon Apr 29 01:23:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505138322862651.1791292068056; Mon, 11 Sep 2017 06:58:42 -0700 (PDT) Received: from localhost ([::1]:57940 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drPEY-0007Yd-8c for importer@patchew.org; Mon, 11 Sep 2017 09:58:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41804) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drP8F-0001pK-Lw for qemu-devel@nongnu.org; Mon, 11 Sep 2017 09:52:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1drP8E-0002K4-Sv for qemu-devel@nongnu.org; Mon, 11 Sep 2017 09:52:11 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1drP86-00023m-NY; Mon, 11 Sep 2017 09:52:02 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7s-0007me-8q; Mon, 11 Sep 2017 14:51:48 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 11 Sep 2017 14:52:08 +0100 Message-Id: <1505137930-13255-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 5/7] target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In do_v7m_exception_exit(), there's no need to force the high 4 bits of 'type' to 1 when calling v7m_exception_taken(), because we know that they're always 1 or we could not have got to this "handle return to magic exception return address" code. Remove the unnecessary ORs. Signed-off-by: Peter Maydell Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 1741e0d..fdd5cc6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6306,7 +6306,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) */ env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - v7m_exception_taken(cpu, type | 0xf0000000); + v7m_exception_taken(cpu, type); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " "stackframe: failed exception return integrity check= \n"); return; @@ -6348,7 +6348,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; v7m_push_stack(cpu); - v7m_exception_taken(cpu, type | 0xf0000000); + v7m_exception_taken(cpu, type); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe= : " "failed exception return integrity check\n"); return; --=20 2.7.4 From nobody Mon Apr 29 01:23:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505138273155612.8529516428025; Mon, 11 Sep 2017 06:57:53 -0700 (PDT) Received: from localhost ([::1]:57937 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drPDk-0006pz-FL for importer@patchew.org; Mon, 11 Sep 2017 09:57:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41737) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drP88-0001iB-Fi for qemu-devel@nongnu.org; Mon, 11 Sep 2017 09:52:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1drP87-0002Ew-Ij for qemu-devel@nongnu.org; Mon, 11 Sep 2017 09:52:04 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1drP82-00023m-0L; Mon, 11 Sep 2017 09:51:58 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7s-0007mr-VD; Mon, 11 Sep 2017 14:51:48 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 11 Sep 2017 14:52:09 +0100 Message-Id: <1505137930-13255-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 6/7] target/arm: Add and use defines for EXCRET constants X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The exception-return magic values get some new bits in v8M, which makes some bit definitions for them worthwhile. We don't use the bit definitions for the switch on the low bits which checks the return type for v7M, because this is defined in the v7M ARM ARM as a set of valid values rather than via per-bit checks. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis --- target/arm/internals.h | 10 ++++++++++ target/arm/helper.c | 14 +++++++++----- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a315354..18be370 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -61,6 +61,16 @@ FIELD(V7M_CONTROL, NPRIV, 0, 1) FIELD(V7M_CONTROL, SPSEL, 1, 1) FIELD(V7M_CONTROL, FPCA, 2, 1) =20 +/* Bit definitions for v7M exception return payload */ +FIELD(V7M_EXCRET, ES, 0, 1) +FIELD(V7M_EXCRET, RES0, 1, 1) +FIELD(V7M_EXCRET, SPSEL, 2, 1) +FIELD(V7M_EXCRET, MODE, 3, 1) +FIELD(V7M_EXCRET, FTYPE, 4, 1) +FIELD(V7M_EXCRET, DCRS, 5, 1) +FIELD(V7M_EXCRET, S, 6, 1) +FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */ + /* * For AArch64, map a given EL to an index in the banked_spsr array. * Note that this mapping and the AArch32 mapping defined in bank_number() diff --git a/target/arm/helper.c b/target/arm/helper.c index fdd5cc6..a502e4e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6242,7 +6242,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) " previous exception %d\n", type, env->v7m.exception); =20 - if (extract32(type, 5, 23) !=3D extract32(-1, 5, 23)) { + if ((type & R_V7M_EXCRET_RES1_MASK) !=3D R_V7M_EXCRET_RES1_MASK) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in excep= tion " "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", t= ype); } @@ -6255,7 +6255,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) */ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - int es =3D type & 1; + int es =3D type & R_V7M_EXCRET_ES_MASK; if (armv7m_nvic_raw_execution_priority(env->nvic) >=3D 0) { env->v7m.faultmask[es] =3D 0; } @@ -6491,12 +6491,16 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) return; /* Never happens. Keep compiler happy. */ } =20 - lr =3D 0xfffffff1; + lr =3D R_V7M_EXCRET_RES1_MASK | + R_V7M_EXCRET_S_MASK | + R_V7M_EXCRET_DCRS_MASK | + R_V7M_EXCRET_FTYPE_MASK | + R_V7M_EXCRET_ES_MASK; if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { - lr |=3D 4; + lr |=3D R_V7M_EXCRET_SPSEL_MASK; } if (!arm_v7m_is_handler_mode(env)) { - lr |=3D 8; + lr |=3D R_V7M_EXCRET_MODE_MASK; } =20 v7m_push_stack(cpu); --=20 2.7.4 From nobody Mon Apr 29 01:23:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1505138040652538.3720434090835; Mon, 11 Sep 2017 06:54:00 -0700 (PDT) Received: from localhost ([::1]:57907 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drP9z-0003DG-4A for importer@patchew.org; Mon, 11 Sep 2017 09:53:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41651) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1drP84-0001dh-Bk for qemu-devel@nongnu.org; Mon, 11 Sep 2017 09:52:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1drP83-0002Bi-E9 for qemu-devel@nongnu.org; Mon, 11 Sep 2017 09:52:00 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37238) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1drP81-00023m-0r; Mon, 11 Sep 2017 09:51:57 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1drP7t-0007nI-Lz; Mon, 11 Sep 2017 14:51:49 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 11 Sep 2017 14:52:10 +0100 Message-Id: <1505137930-13255-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> References: <1505137930-13255-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 7/7] target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In the v7M and v8M ARM ARM, the magic exception return values are referred to as EXC_RETURN values, and in QEMU we use V7M_EXCRET_* constants to define bits within them. Rename the 'type' variable which holds the exception return value in do_v7m_exception_exit() to excret, making it clearer that it does hold an EXC_RETURN value. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a502e4e..4f41841 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6212,7 +6212,7 @@ static void v7m_push_stack(ARMCPU *cpu) static void do_v7m_exception_exit(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; - uint32_t type; + uint32_t excret; uint32_t xpsr; bool ufault =3D false; bool return_to_sp_process =3D false; @@ -6233,18 +6233,19 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * the target value up between env->regs[15] and env->thumb in * gen_bx(). Reconstitute it. */ - type =3D env->regs[15]; + excret =3D env->regs[15]; if (env->thumb) { - type |=3D 1; + excret |=3D 1; } =20 qemu_log_mask(CPU_LOG_INT, "Exception return: magic PC %" PRIx32 " previous exception %d\n", - type, env->v7m.exception); + excret, env->v7m.exception); =20 - if ((type & R_V7M_EXCRET_RES1_MASK) !=3D R_V7M_EXCRET_RES1_MASK) { + if ((excret & R_V7M_EXCRET_RES1_MASK) !=3D R_V7M_EXCRET_RES1_MASK) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero high bits in excep= tion " - "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", t= ype); + "exit PC value 0x%" PRIx32 " are UNPREDICTABLE\n", + excret); } =20 if (env->v7m.exception !=3D ARMV7M_EXCP_NMI) { @@ -6255,7 +6256,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) */ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - int es =3D type & R_V7M_EXCRET_ES_MASK; + int es =3D excret & R_V7M_EXCRET_ES_MASK; if (armv7m_nvic_raw_execution_priority(env->nvic) >=3D 0) { env->v7m.faultmask[es] =3D 0; } @@ -6283,7 +6284,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) g_assert_not_reached(); } =20 - switch (type & 0xf) { + switch (excret & 0xf) { case 1: /* Return to Handler */ return_to_handler =3D true; break; @@ -6306,7 +6307,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) */ env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - v7m_exception_taken(cpu, type); + v7m_exception_taken(cpu, excret); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " "stackframe: failed exception return integrity check= \n"); return; @@ -6341,14 +6342,14 @@ static void do_v7m_exception_exit(ARMCPU *cpu) =20 /* The restored xPSR exception field will be zero if we're * resuming in Thread mode. If that doesn't match what the - * exception return type specified then this is a UsageFault. + * exception return excret specified then this is a UsageFault. */ if (return_to_handler !=3D arm_v7m_is_handler_mode(env)) { /* Take an INVPC UsageFault by pushing the stack again. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; v7m_push_stack(cpu); - v7m_exception_taken(cpu, type); + v7m_exception_taken(cpu, excret); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe= : " "failed exception return integrity check\n"); return; --=20 2.7.4