From nobody Mon Feb 9 18:19:34 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504791523675648.7341447860083; Thu, 7 Sep 2017 06:38:43 -0700 (PDT) Received: from localhost ([::1]:40531 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpx10-0001Jz-3t for importer@patchew.org; Thu, 07 Sep 2017 09:38:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56430) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpwr2-0000zz-NN for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpwqw-0007cg-GX for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:24 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37190) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dpwqw-0007ak-6B for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:18 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dpwqn-0001YR-9V for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:28:09 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 14:28:01 +0100 Message-Id: <1504790904-17018-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504790904-17018-1-git-send-email-peter.maydell@linaro.org> References: <1504790904-17018-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 08/31] target/arm: Implement ARMv8M's PMSAv8 registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As part of ARMv8M, we need to add support for the PMSAv8 MPU architecture. PMSAv8 differs from PMSAv7 both in register/data layout (for instance using base and limit registers rather than base and size) and also in behaviour (for example it does not have subregions); rather than trying to wedge it into the existing PMSAv7 code and data structures, we define separate ones. This commit adds the data structures which hold the state for a PMSAv8 MPU and the register interface to it. The implementation of the MPU behaviour will be added in a subsequent commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1503414539-28762-2-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 13 ++++++ hw/intc/armv7m_nvic.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++= ---- target/arm/cpu.c | 36 ++++++++++----- target/arm/machine.c | 29 +++++++++++- 4 files changed, 180 insertions(+), 20 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 92771d3..9fd5de7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -522,6 +522,19 @@ typedef struct CPUARMState { uint32_t rnr; } pmsav7; =20 + /* PMSAv8 MPU */ + struct { + /* The PMSAv8 implementation also shares some PMSAv7 config + * and state: + * pmsav7.rnr (region number register) + * pmsav7_dregion (number of configured regions) + */ + uint32_t *rbar; + uint32_t *rlar; + uint32_t mair0; + uint32_t mair1; + } pmsav8; + void *nvic; const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index bbfe2d5..c0dbbad 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -544,25 +544,67 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set) { int region =3D cpu->env.pmsav7.rnr; =20 + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* PMSAv8M handling of the aliases is different from v7M: + * aliases A1, A2, A3 override the low two bits of the region + * number in MPU_RNR, and there is no 'region' field in the + * RBAR register. + */ + int aliasno =3D (offset - 0xd9c) / 8; /* 0..3 */ + if (aliasno) { + region =3D deposit32(region, 0, 2, aliasno); + } + if (region >=3D cpu->pmsav7_dregion) { + return 0; + } + return cpu->env.pmsav8.rbar[region]; + } + if (region >=3D cpu->pmsav7_dregion) { return 0; } return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf); } - case 0xda0: /* MPU_RASR */ - case 0xda8: /* MPU_RASR_A1 */ - case 0xdb0: /* MPU_RASR_A2 */ - case 0xdb8: /* MPU_RASR_A3 */ + case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ + case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ + case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ + case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ { int region =3D cpu->env.pmsav7.rnr; =20 + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* PMSAv8M handling of the aliases is different from v7M: + * aliases A1, A2, A3 override the low two bits of the region + * number in MPU_RNR. + */ + int aliasno =3D (offset - 0xda0) / 8; /* 0..3 */ + if (aliasno) { + region =3D deposit32(region, 0, 2, aliasno); + } + if (region >=3D cpu->pmsav7_dregion) { + return 0; + } + return cpu->env.pmsav8.rlar[region]; + } + if (region >=3D cpu->pmsav7_dregion) { return 0; } return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) | (cpu->env.pmsav7.drsr[region] & 0xffff); } + case 0xdc0: /* MPU_MAIR0 */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + return cpu->env.pmsav8.mair0; + case 0xdc4: /* MPU_MAIR1 */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + return cpu->env.pmsav8.mair1; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", off= set); return 0; } @@ -691,6 +733,26 @@ static void nvic_writel(NVICState *s, uint32_t offset,= uint32_t value) { int region; =20 + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* PMSAv8M handling of the aliases is different from v7M: + * aliases A1, A2, A3 override the low two bits of the region + * number in MPU_RNR, and there is no 'region' field in the + * RBAR register. + */ + int aliasno =3D (offset - 0xd9c) / 8; /* 0..3 */ + + region =3D cpu->env.pmsav7.rnr; + if (aliasno) { + region =3D deposit32(region, 0, 2, aliasno); + } + if (region >=3D cpu->pmsav7_dregion) { + return; + } + cpu->env.pmsav8.rbar[region] =3D value; + tlb_flush(CPU(cpu)); + return; + } + if (value & (1 << 4)) { /* VALID bit means use the region number specified in this * value and also update MPU_RNR.REGION with that value. @@ -715,13 +777,32 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value) tlb_flush(CPU(cpu)); break; } - case 0xda0: /* MPU_RASR */ - case 0xda8: /* MPU_RASR_A1 */ - case 0xdb0: /* MPU_RASR_A2 */ - case 0xdb8: /* MPU_RASR_A3 */ + case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ + case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ + case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ + case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ { int region =3D cpu->env.pmsav7.rnr; =20 + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* PMSAv8M handling of the aliases is different from v7M: + * aliases A1, A2, A3 override the low two bits of the region + * number in MPU_RNR. + */ + int aliasno =3D (offset - 0xd9c) / 8; /* 0..3 */ + + region =3D cpu->env.pmsav7.rnr; + if (aliasno) { + region =3D deposit32(region, 0, 2, aliasno); + } + if (region >=3D cpu->pmsav7_dregion) { + return; + } + cpu->env.pmsav8.rlar[region] =3D value; + tlb_flush(CPU(cpu)); + return; + } + if (region >=3D cpu->pmsav7_dregion) { return; } @@ -731,6 +812,30 @@ static void nvic_writel(NVICState *s, uint32_t offset,= uint32_t value) tlb_flush(CPU(cpu)); break; } + case 0xdc0: /* MPU_MAIR0 */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + if (cpu->pmsav7_dregion) { + /* Register is RES0 if no MPU regions are implemented */ + cpu->env.pmsav8.mair0 =3D value; + } + /* We don't need to do anything else because memory attributes + * only affect cacheability, and we don't implement caching. + */ + break; + case 0xdc4: /* MPU_MAIR1 */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + if (cpu->pmsav7_dregion) { + /* Register is RES0 if no MPU regions are implemented */ + cpu->env.pmsav8.mair1 =3D value; + } + /* We don't need to do anything else because memory attributes + * only affect cacheability, and we don't implement caching. + */ + break; case 0xf00: /* Software Triggered Interrupt Register */ { int excnum =3D (value & 0x1ff) + NVIC_FIRST_IRQ; @@ -740,6 +845,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value) break; } default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad write offset 0x%x\n", offset); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 41ae6ba..8b610de 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -228,17 +228,25 @@ static void arm_cpu_reset(CPUState *s) env->vfp.xregs[ARM_VFP_FPEXC] =3D 0; #endif =20 - if (arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V7)) { + if (arm_feature(env, ARM_FEATURE_PMSA)) { if (cpu->pmsav7_dregion > 0) { - memset(env->pmsav7.drbar, 0, - sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); - memset(env->pmsav7.drsr, 0, - sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); - memset(env->pmsav7.dracr, 0, - sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); + if (arm_feature(env, ARM_FEATURE_V8)) { + memset(env->pmsav8.rbar, 0, + sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion); + memset(env->pmsav8.rlar, 0, + sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion); + } else if (arm_feature(env, ARM_FEATURE_V7)) { + memset(env->pmsav7.drbar, 0, + sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); + memset(env->pmsav7.drsr, 0, + sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); + memset(env->pmsav7.dracr, 0, + sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); + } } env->pmsav7.rnr =3D 0; + env->pmsav8.mair0 =3D 0; + env->pmsav8.mair1 =3D 0; } =20 set_flush_to_zero(1, &env->vfp.standard_fp_status); @@ -809,9 +817,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) } =20 if (nr) { - env->pmsav7.drbar =3D g_new0(uint32_t, nr); - env->pmsav7.drsr =3D g_new0(uint32_t, nr); - env->pmsav7.dracr =3D g_new0(uint32_t, nr); + if (arm_feature(env, ARM_FEATURE_V8)) { + /* PMSAv8 */ + env->pmsav8.rbar =3D g_new0(uint32_t, nr); + env->pmsav8.rlar =3D g_new0(uint32_t, nr); + } else { + env->pmsav7.drbar =3D g_new0(uint32_t, nr); + env->pmsav7.drsr =3D g_new0(uint32_t, nr); + env->pmsav7.dracr =3D g_new0(uint32_t, nr); + } } } =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index 3193b00..7b6f9de 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -159,7 +159,8 @@ static bool pmsav7_needed(void *opaque) CPUARMState *env =3D &cpu->env; =20 return arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V7); + arm_feature(env, ARM_FEATURE_V7) && + !arm_feature(env, ARM_FEATURE_V8); } =20 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) @@ -209,6 +210,31 @@ static const VMStateDescription vmstate_pmsav7_rnr =3D= { } }; =20 +static bool pmsav8_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8); +} + +static const VMStateDescription vmstate_pmsav8 =3D { + .name =3D "cpu/pmsav8", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pmsav8_needed, + .fields =3D (VMStateField[]) { + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_UINT32(env.pmsav8.mair0, ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair1, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static int get_cpsr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { @@ -458,6 +484,7 @@ const VMStateDescription vmstate_arm_cpu =3D { */ &vmstate_pmsav7_rnr, &vmstate_pmsav7, + &vmstate_pmsav8, NULL } }; --=20 2.7.4