From nobody Thu Dec 18 13:18:48 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504791910041218.65802281693323; Thu, 7 Sep 2017 06:45:10 -0700 (PDT) Received: from localhost ([::1]:40556 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpx7E-0007KZ-KO for importer@patchew.org; Thu, 07 Sep 2017 09:45:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56379) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpwqz-0000zg-Gv for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpwqu-0007bK-EA for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:21 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37190) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dpwqu-0007ak-63 for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:16 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dpwqt-0001c8-5B for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:28:15 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 14:28:10 +0100 Message-Id: <1504790904-17018-18-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504790904-17018-1-git-send-email-peter.maydell@linaro.org> References: <1504790904-17018-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 17/31] nvic: Add NS alias SCS region X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For v8M the range 0xe002e000..0xe002efff is an alias region which for secure accesses behaves like a NonSecure access to the main SCS region. (For nonsecure accesses including when the security extension is not implemented, it is RAZ/WI.) Signed-off-by: Peter Maydell Message-id: 1503414539-28762-11-git-send-email-peter.maydell@linaro.org --- include/hw/intc/armv7m_nvic.h | 1 + hw/intc/armv7m_nvic.c | 66 +++++++++++++++++++++++++++++++++++++++= +++- 2 files changed, 66 insertions(+), 1 deletion(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 1d145fb..1a4cce7 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -50,6 +50,7 @@ typedef struct NVICState { int exception_prio; /* group prio of the highest prio active exception= */ =20 MemoryRegion sysregmem; + MemoryRegion sysreg_ns_mem; MemoryRegion container; =20 uint32_t num_irq; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index babdc3b..2b0b328 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1040,6 +1040,47 @@ static const MemoryRegionOps nvic_sysreg_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + if (attrs.secure) { + /* S accesses to the alias act like NS accesses to the real region= */ + attrs.secure =3D 0; + return nvic_sysreg_write(opaque, addr, value, size, attrs); + } else { + /* NS attrs are RAZ/WI for privileged, and BusFault for user */ + if (attrs.user) { + return MEMTX_ERROR; + } + return MEMTX_OK; + } +} + +static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + if (attrs.secure) { + /* S accesses to the alias act like NS accesses to the real region= */ + attrs.secure =3D 0; + return nvic_sysreg_read(opaque, addr, data, size, attrs); + } else { + /* NS attrs are RAZ/WI for privileged, and BusFault for user */ + if (attrs.user) { + return MEMTX_ERROR; + } + *data =3D 0; + return MEMTX_OK; + } +} + +static const MemoryRegionOps nvic_sysreg_ns_ops =3D { + .read_with_attrs =3D nvic_sysreg_ns_read, + .write_with_attrs =3D nvic_sysreg_ns_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + static int nvic_post_load(void *opaque, int version_id) { NVICState *s =3D opaque; @@ -1141,6 +1182,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Err= or **errp) NVICState *s =3D NVIC(dev); SysBusDevice *systick_sbd; Error *err =3D NULL; + int regionlen; =20 s->cpu =3D ARM_CPU(qemu_get_cpu(0)); assert(s->cpu); @@ -1173,8 +1215,23 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) * 0xd00..0xd3c - SCS registers * 0xd40..0xeff - Reserved or Not implemented * 0xf00 - STIR + * + * Some registers within this space are banked between security states. + * In v8M there is a second range 0xe002e000..0xe002efff which is the + * NonSecure alias SCS; secure accesses to this behave like NS accesses + * to the main SCS range, and non-secure accesses (including when + * the security extension is not implemented) are RAZ/WI. + * Note that both the main SCS range and the alias range are defined + * to be exempt from memory attribution (R_BLJT) and so the memory + * transaction attribute always matches the current CPU security + * state (attrs.secure =3D=3D env->v7m.secure). In the nvic_sysreg_ns_= ops + * wrappers we change attrs.secure to indicate the NS access; so + * generally code determining which banked register to use should + * use attrs.secure; code determining actual behaviour of the system + * should use env->v7m.secure. */ - memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000); + regionlen =3D arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x= 1000; + memory_region_init(&s->container, OBJECT(s), "nvic", regionlen); /* The system register region goes at the bottom of the priority * stack as it covers the whole page. */ @@ -1185,6 +1242,13 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) sysbus_mmio_get_region(systick_sbd= , 0), 1); =20 + if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { + memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), + &nvic_sysreg_ns_ops, s, + "nvic_sysregs_ns", 0x1000); + memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_= mem); + } + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); } =20 --=20 2.7.4