From nobody Tue Feb 10 02:43:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504792193809381.27554536481057; Thu, 7 Sep 2017 06:49:53 -0700 (PDT) Received: from localhost ([::1]:40572 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpxBj-0003IS-Qf for importer@patchew.org; Thu, 07 Sep 2017 09:49:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56463) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpwr3-00010B-KL for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpwqt-0007as-Qr for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:25 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37186) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dpwqt-0007Xf-Iq for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:15 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dpwqs-0001bg-GR for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:28:14 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 14:28:09 +0100 Message-Id: <1504790904-17018-17-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504790904-17018-1-git-send-email-peter.maydell@linaro.org> References: <1504790904-17018-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 16/31] target/arm: Make CONTROL register banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the CONTROL register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1503414539-28762-10-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 5 +++-- target/arm/helper.c | 21 +++++++++++---------- target/arm/machine.c | 3 ++- target/arm/translate.c | 2 +- 4 files changed, 17 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5cf2e76..1d9eb36 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -422,7 +422,7 @@ typedef struct CPUARMState { uint32_t other_sp; uint32_t vecbase; uint32_t basepri[2]; - uint32_t control; + uint32_t control[2]; uint32_t ccr; /* Configuration and Control */ uint32_t cfsr; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ @@ -1681,7 +1681,8 @@ static inline bool arm_v7m_is_handler_mode(CPUARMStat= e *env) static inline int arm_current_el(CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_M)) { - return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1); + return arm_v7m_is_handler_mode(env) || + !(env->v7m.control[env->v7m.secure] & 1); } =20 if (is_a64(env)) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 4f53ea1..aa64596 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6048,14 +6048,15 @@ static uint32_t v7m_pop(CPUARMState *env) static void switch_v7m_sp(CPUARMState *env, bool new_spsel) { uint32_t tmp; - bool old_spsel =3D env->v7m.control & R_V7M_CONTROL_SPSEL_MASK; + uint32_t old_control =3D env->v7m.control[env->v7m.secure]; + bool old_spsel =3D old_control & R_V7M_CONTROL_SPSEL_MASK; =20 if (old_spsel !=3D new_spsel) { tmp =3D env->v7m.other_sp; env->v7m.other_sp =3D env->regs[13]; env->regs[13] =3D tmp; =20 - env->v7m.control =3D deposit32(env->v7m.control, + env->v7m.control[env->v7m.secure] =3D deposit32(old_control, R_V7M_CONTROL_SPSEL_SHIFT, R_V7M_CONTROL_SPSEL_LENGTH, new_spsel= ); } @@ -6409,7 +6410,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) } =20 lr =3D 0xfffffff1; - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { lr |=3D 4; } if (!arm_v7m_is_handler_mode(env)) { @@ -8827,7 +8828,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t r= eg) return xpsr_read(env) & mask; break; case 20: /* CONTROL */ - return env->v7m.control; + return env->v7m.control[env->v7m.secure]; } =20 if (el =3D=3D 0) { @@ -8836,10 +8837,10 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t= reg) =20 switch (reg) { case 8: /* MSP */ - return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? + return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MA= SK) ? env->v7m.other_sp : env->regs[13]; case 9: /* PSP */ - return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? + return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MA= SK) ? env->regs[13] : env->v7m.other_sp; case 16: /* PRIMASK */ return env->v7m.primask[env->v7m.secure]; @@ -8888,14 +8889,14 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t mas= kreg, uint32_t val) } break; case 8: /* MSP */ - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { env->v7m.other_sp =3D val; } else { env->regs[13] =3D val; } break; case 9: /* PSP */ - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { env->regs[13] =3D val; } else { env->v7m.other_sp =3D val; @@ -8926,8 +8927,8 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) if (!arm_v7m_is_handler_mode(env)) { switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) !=3D 0); } - env->v7m.control &=3D ~R_V7M_CONTROL_NPRIV_MASK; - env->v7m.control |=3D val & R_V7M_CONTROL_NPRIV_MASK; + env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_MASK; + env->v7m.control[env->v7m.secure] |=3D val & R_V7M_CONTROL_NPRIV_M= ASK; break; default: qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" diff --git a/target/arm/machine.c b/target/arm/machine.c index 94f7279..5e379ed 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -116,7 +116,7 @@ static const VMStateDescription vmstate_m =3D { .fields =3D (VMStateField[]) { VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), - VMSTATE_UINT32(env.v7m.control, ARMCPU), + VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.ccr, ARMCPU), VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), @@ -253,6 +253,7 @@ static const VMStateDescription vmstate_m_security =3D { VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; diff --git a/target/arm/translate.c b/target/arm/translate.c index dea0a6f..6aa2d7c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12241,7 +12241,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fpri= ntf_function cpu_fprintf, if (xpsr & XPSR_EXCP) { mode =3D "handler"; } else { - if (env->v7m.control & R_V7M_CONTROL_NPRIV_MASK) { + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MA= SK) { mode =3D "unpriv-thread"; } else { mode =3D "priv-thread"; --=20 2.7.4