From nobody Tue Feb 10 02:43:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504791190336796.0841860539455; Thu, 7 Sep 2017 06:33:10 -0700 (PDT) Received: from localhost ([::1]:40511 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpwvd-0004bs-4H for importer@patchew.org; Thu, 07 Sep 2017 09:33:09 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56402) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpwr1-0000zl-In for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpwqv-0007bx-Ar for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:23 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37190) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dpwqv-0007ak-3z for qemu-devel@nongnu.org; Thu, 07 Sep 2017 09:28:17 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dpwqp-0001Zi-6U for qemu-devel@nongnu.org; Thu, 07 Sep 2017 14:28:11 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 14:28:04 +0100 Message-Id: <1504790904-17018-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504790904-17018-1-git-send-email-peter.maydell@linaro.org> References: <1504790904-17018-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/31] target/arm: Register second AddressSpace for secure v8M CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If a v8M CPU supports the security extension then we need to give it two AddressSpaces, the same way we do already for an A profile core with EL3. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1503414539-28762-5-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f32317e..ae866be 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -843,22 +843,21 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) init_cpreg_list(cpu); =20 #ifndef CONFIG_USER_ONLY - if (cpu->has_el3) { - cs->num_ases =3D 2; - } else { - cs->num_ases =3D 1; - } - - if (cpu->has_el3) { + if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { AddressSpace *as; =20 + cs->num_ases =3D 2; + if (!cpu->secure_memory) { cpu->secure_memory =3D cs->memory; } as =3D address_space_init_shareable(cpu->secure_memory, "cpu-secure-memory"); cpu_address_space_init(cs, as, ARMASIdx_S); + } else { + cs->num_ases =3D 1; } + cpu_address_space_init(cs, address_space_init_shareable(cs->memory, "cpu-memory"), --=20 2.7.4