From nobody Sun May 5 03:23:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504627011843975.2587169408225; Tue, 5 Sep 2017 08:56:51 -0700 (PDT) Received: from localhost ([::1]:59794 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpGDa-0002h5-SH for importer@patchew.org; Tue, 05 Sep 2017 11:56:50 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59240) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpGAY-0000MV-Re for qemu-devel@nongnu.org; Tue, 05 Sep 2017 11:53:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpGAT-0004HU-U9 for qemu-devel@nongnu.org; Tue, 05 Sep 2017 11:53:42 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37160) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dpGAJ-00045L-At; Tue, 05 Sep 2017 11:53:27 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dpGA8-00079N-Cr; Tue, 05 Sep 2017 16:53:16 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 5 Sep 2017 16:53:32 +0100 Message-Id: <1504626814-23124-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504626814-23124-1-git-send-email-peter.maydell@linaro.org> References: <1504626814-23124-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH v2 1/3] boards.h: Define new flag ignore_memory_transaction_failures X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Define a new MachineClass field ignore_memory_transaction_failures. If this is flag is true then the CPU will ignore memory transaction failures which should cause the CPU to take an exception due to an access to an unassigned physical address; the transaction will instead return zero (for a read) or be ignored (for a write). This should be set only by legacy board models which rely on the old RAZ/WI behaviour for handling devices that QEMU does not yet model. New board models should instead use "unimplemented-device" for all memory ranges where the guest will attempt to probe for a device that QEMU doesn't implement and a stub device is required. We need this for ARM boards, where we're about to implement support for generating external aborts on memory transaction failures. Too many of our legacy board models rely on the RAZ/WI behaviour and we would break currently working guests when their "probe for device" code provoked an external abort rather than a RAZ. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- include/hw/boards.h | 11 +++++++++++ include/qom/cpu.h | 7 ++++++- qom/cpu.c | 16 ++++++++++++++++ 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index 3363dd1..7f044d1 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -131,6 +131,16 @@ typedef struct { * size than the target architecture's minimum. (Attempting to create * such a CPU will fail.) Note that changing this is a migration * compatibility break for the machine. + * @ignore_memory_transaction_failures: + * If this is flag is true then the CPU will ignore memory transaction + * failures which should cause the CPU to take an exception due to an + * access to an unassigned physical address; the transaction will inste= ad + * return zero (for a read) or be ignored (for a write). This should be + * set only by legacy board models which rely on the old RAZ/WI behavio= ur + * for handling devices that QEMU does not yet model. New board models + * should instead use "unimplemented-device" for all memory ranges where + * the guest will attempt to probe for a device that QEMU doesn't + * implement and a stub device is required. */ struct MachineClass { /*< private >*/ @@ -171,6 +181,7 @@ struct MachineClass { bool rom_file_has_mr; int minimum_page_bits; bool has_hotpluggable_cpus; + bool ignore_memory_transaction_failures; int numa_mem_align_shift; void (*numa_auto_assign_ram)(MachineClass *mc, NodeInfo *nodes, int nb_nodes, ram_addr_t size); diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 08bd868..995a7be 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -312,6 +312,9 @@ struct qemu_work_item; * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all ch= anges * to @trace_dstate). * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). + * @ignore_memory_transaction_failures: Cached copy of the MachineState + * flag of the same name: allows the board to suppress calling of the + * CPU do_transaction_failed hook function. * * State of one CPU core or thread. */ @@ -398,6 +401,8 @@ struct CPUState { */ bool throttle_thread_scheduled; =20 + bool ignore_memory_transaction_failures; + /* Note that this is accessed at the start of every TB via a negative offset from AREG0. Leave this field at the end so as to make the (absolute value) offset as small as possible. This reduces code @@ -864,7 +869,7 @@ static inline void cpu_transaction_failed(CPUState *cpu= , hwaddr physaddr, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->do_transaction_failed) { + if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_fai= led) { cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, mmu_idx, attrs, response, retaddr); } diff --git a/qom/cpu.c b/qom/cpu.c index deb8880..dc5392d 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -29,6 +29,7 @@ #include "exec/cpu-common.h" #include "qemu/error-report.h" #include "sysemu/sysemu.h" +#include "hw/boards.h" #include "hw/qdev-properties.h" #include "trace-root.h" =20 @@ -363,6 +364,21 @@ static void cpu_common_parse_features(const char *type= name, char *features, static void cpu_common_realizefn(DeviceState *dev, Error **errp) { CPUState *cpu =3D CPU(dev); + Object *machine =3D qdev_get_machine(); + + /* qdev_get_machine() can return something that's not TYPE_MACHINE + * if this is one of the user-only emulators; in that case there's + * no need to check the ignore_memory_transaction_failures board flag. + */ + if (object_dynamic_cast(machine, TYPE_MACHINE)) { + ObjectClass *oc =3D object_get_class(machine); + MachineClass *mc =3D MACHINE_CLASS(oc); + + if (mc) { + cpu->ignore_memory_transaction_failures =3D + mc->ignore_memory_transaction_failures; + } + } =20 if (dev->hotplugged) { cpu_synchronize_post_init(cpu); --=20 2.7.4 From nobody Sun May 5 03:23:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1504626945514848.2527032423283; Tue, 5 Sep 2017 08:55:45 -0700 (PDT) Received: from localhost ([::1]:59788 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpGCW-0001mp-EG for importer@patchew.org; Tue, 05 Sep 2017 11:55:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59316) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpGAc-0000PW-MG for qemu-devel@nongnu.org; Tue, 05 Sep 2017 11:53:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpGAW-0004J9-Vx for qemu-devel@nongnu.org; Tue, 05 Sep 2017 11:53:46 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37160) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dpGAK-00045L-B9; Tue, 05 Sep 2017 11:53:28 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dpGA9-00079b-1x; Tue, 05 Sep 2017 16:53:17 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 5 Sep 2017 16:53:33 +0100 Message-Id: <1504626814-23124-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504626814-23124-1-git-send-email-peter.maydell@linaro.org> References: <1504626814-23124-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH v2 2/3] hw/arm: Set ignore_memory_transaction_failures for most ARM boards X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Set the MachineClass flag ignore_memory_transaction_failures for almost all ARM boards. This means they retain the legacy behaviour that accesses to unimplemented addresses will RAZ/WI rather than aborting, when a subsequent commit adds support for external aborts. The exceptions are: * virt -- we know that guests won't try to prod devices that we don't describe in the device tree or ACPI tables * mps2 -- this board was written to use unimplemented-device for all the ranges with devices we don't yet handle New boards should not set the flag, but instead be written like the mps2. Signed-off-by: Peter Maydell For the Xilinx boards: Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis --- hw/arm/aspeed.c | 3 +++ hw/arm/collie.c | 1 + hw/arm/cubieboard.c | 1 + hw/arm/digic_boards.c | 1 + hw/arm/exynos4_boards.c | 2 ++ hw/arm/gumstix.c | 2 ++ hw/arm/highbank.c | 2 ++ hw/arm/imx25_pdk.c | 1 + hw/arm/integratorcp.c | 1 + hw/arm/kzm.c | 1 + hw/arm/mainstone.c | 1 + hw/arm/musicpal.c | 1 + hw/arm/netduino2.c | 1 + hw/arm/nseries.c | 2 ++ hw/arm/omap_sx1.c | 2 ++ hw/arm/palm.c | 1 + hw/arm/raspi.c | 1 + hw/arm/realview.c | 4 ++++ hw/arm/sabrelite.c | 1 + hw/arm/spitz.c | 4 ++++ hw/arm/stellaris.c | 2 ++ hw/arm/tosa.c | 1 + hw/arm/versatilepb.c | 2 ++ hw/arm/vexpress.c | 1 + hw/arm/xilinx_zynq.c | 1 + hw/arm/xlnx-ep108.c | 2 ++ hw/arm/z2.c | 1 + 27 files changed, 43 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 0c5635f..ab895ad 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -270,6 +270,7 @@ static void palmetto_bmc_class_init(ObjectClass *oc, vo= id *data) mc->no_floppy =3D 1; mc->no_cdrom =3D 1; mc->no_parallel =3D 1; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo palmetto_bmc_type =3D { @@ -302,6 +303,7 @@ static void ast2500_evb_class_init(ObjectClass *oc, voi= d *data) mc->no_floppy =3D 1; mc->no_cdrom =3D 1; mc->no_parallel =3D 1; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo ast2500_evb_type =3D { @@ -326,6 +328,7 @@ static void romulus_bmc_class_init(ObjectClass *oc, voi= d *data) mc->no_floppy =3D 1; mc->no_cdrom =3D 1; mc->no_parallel =3D 1; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo romulus_bmc_type =3D { diff --git a/hw/arm/collie.c b/hw/arm/collie.c index 2e69531..8830192 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -64,6 +64,7 @@ static void collie_machine_init(MachineClass *mc) { mc->desc =3D "Sharp SL-5500 (Collie) PDA (SA-1110)"; mc->init =3D collie_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("collie", collie_machine_init) diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index b98e1c4..32f1edd 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -86,6 +86,7 @@ static void cubieboard_machine_init(MachineClass *mc) mc->init =3D cubieboard_init; mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("cubieboard", cubieboard_machine_init) diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 520c8e9..9f11dcd 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -155,6 +155,7 @@ static void canon_a1100_machine_init(MachineClass *mc) { mc->desc =3D "Canon PowerShot A1100 IS"; mc->init =3D &canon_a1100_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("canon-a1100", canon_a1100_machine_init) diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 7c03ed3..f1441ec 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -189,6 +189,7 @@ static void nuri_class_init(ObjectClass *oc, void *data) mc->desc =3D "Samsung NURI board (Exynos4210)"; mc->init =3D nuri_init; mc->max_cpus =3D EXYNOS4210_NCPUS; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo nuri_type =3D { @@ -204,6 +205,7 @@ static void smdkc210_class_init(ObjectClass *oc, void *= data) mc->desc =3D "Samsung SMDKC210 board (Exynos4210)"; mc->init =3D smdkc210_init; mc->max_cpus =3D EXYNOS4210_NCPUS; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo smdkc210_type =3D { diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c index d59d9ba..092ce36 100644 --- a/hw/arm/gumstix.c +++ b/hw/arm/gumstix.c @@ -128,6 +128,7 @@ static void connex_class_init(ObjectClass *oc, void *da= ta) =20 mc->desc =3D "Gumstix Connex (PXA255)"; mc->init =3D connex_init; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo connex_type =3D { @@ -142,6 +143,7 @@ static void verdex_class_init(ObjectClass *oc, void *da= ta) =20 mc->desc =3D "Gumstix Verdex (PXA270)"; mc->init =3D verdex_init; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo verdex_type =3D { diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 942d5a8..ba27789 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -413,6 +413,7 @@ static void highbank_class_init(ObjectClass *oc, void *= data) mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; mc->max_cpus =3D 4; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo highbank_type =3D { @@ -430,6 +431,7 @@ static void midway_class_init(ObjectClass *oc, void *da= ta) mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; mc->max_cpus =3D 4; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo midway_type =3D { diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index 7d42c74..9f3ee14 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -148,6 +148,7 @@ static void imx25_pdk_machine_init(MachineClass *mc) { mc->desc =3D "ARM i.MX25 PDK board (ARM926)"; mc->init =3D imx25_pdk_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init) diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index d9530ed..d603af9 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -681,6 +681,7 @@ static void integratorcp_machine_init(MachineClass *mc) { mc->desc =3D "ARM Integrator/CP (ARM926EJ-S)"; mc->init =3D integratorcp_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("integratorcp", integratorcp_machine_init) diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index 3ed6577..f9c2228 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -142,6 +142,7 @@ static void kzm_machine_init(MachineClass *mc) { mc->desc =3D "ARM KZM Emulation Baseboard (ARM1136)"; mc->init =3D kzm_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("kzm", kzm_machine_init) diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c index fb268e6..637f52c 100644 --- a/hw/arm/mainstone.c +++ b/hw/arm/mainstone.c @@ -196,6 +196,7 @@ static void mainstone2_machine_init(MachineClass *mc) { mc->desc =3D "Mainstone II (PXA27x)"; mc->init =3D mainstone_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("mainstone", mainstone2_machine_init) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index a8b3d46..ab4ba31 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -1718,6 +1718,7 @@ static void musicpal_machine_init(MachineClass *mc) { mc->desc =3D "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; mc->init =3D musicpal_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("musicpal", musicpal_machine_init) diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 3cfe332..9d34d4c 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -45,6 +45,7 @@ static void netduino2_machine_init(MachineClass *mc) { mc->desc =3D "Netduino 2 Machine"; mc->init =3D netduino2_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("netduino2", netduino2_machine_init) diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c index 503a3b6..a32ac82 100644 --- a/hw/arm/nseries.c +++ b/hw/arm/nseries.c @@ -1425,6 +1425,7 @@ static void n800_class_init(ObjectClass *oc, void *da= ta) mc->desc =3D "Nokia N800 tablet aka. RX-34 (OMAP2420)"; mc->init =3D n800_init; mc->default_boot_order =3D ""; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo n800_type =3D { @@ -1440,6 +1441,7 @@ static void n810_class_init(ObjectClass *oc, void *da= ta) mc->desc =3D "Nokia N810 tablet aka. RX-44 (OMAP2420)"; mc->init =3D n810_init; mc->default_boot_order =3D ""; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo n810_type =3D { diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 9809106..4535617 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -223,6 +223,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, = void *data) =20 mc->desc =3D "Siemens SX1 (OMAP310) V2"; mc->init =3D sx1_init_v2; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo sx1_machine_v2_type =3D { @@ -237,6 +238,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, = void *data) =20 mc->desc =3D "Siemens SX1 (OMAP310) V1"; mc->init =3D sx1_init_v1; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo sx1_machine_v1_type =3D { diff --git a/hw/arm/palm.c b/hw/arm/palm.c index 64cf8ca..bf070a2 100644 --- a/hw/arm/palm.c +++ b/hw/arm/palm.c @@ -274,6 +274,7 @@ static void palmte_machine_init(MachineClass *mc) { mc->desc =3D "Palm Tungsten|E aka. Cheetah PDA (OMAP310)"; mc->init =3D palmte_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("cheetah", palmte_machine_init) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 32cdc98..5941c9f 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -168,5 +168,6 @@ static void raspi2_machine_init(MachineClass *mc) mc->no_cdrom =3D 1; mc->max_cpus =3D BCM2836_NCPUS; mc->default_ram_size =3D 1024 * 1024 * 1024; + mc->ignore_memory_transaction_failures =3D true; }; DEFINE_MACHINE("raspi2", raspi2_machine_init) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 2736156..f3a49b6 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -398,6 +398,7 @@ static void realview_eb_class_init(ObjectClass *oc, voi= d *data) mc->desc =3D "ARM RealView Emulation Baseboard (ARM926EJ-S)"; mc->init =3D realview_eb_init; mc->block_default_type =3D IF_SCSI; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo realview_eb_type =3D { @@ -414,6 +415,7 @@ static void realview_eb_mpcore_class_init(ObjectClass *= oc, void *data) mc->init =3D realview_eb_mpcore_init; mc->block_default_type =3D IF_SCSI; mc->max_cpus =3D 4; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo realview_eb_mpcore_type =3D { @@ -428,6 +430,7 @@ static void realview_pb_a8_class_init(ObjectClass *oc, = void *data) =20 mc->desc =3D "ARM RealView Platform Baseboard for Cortex-A8"; mc->init =3D realview_pb_a8_init; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo realview_pb_a8_type =3D { @@ -443,6 +446,7 @@ static void realview_pbx_a9_class_init(ObjectClass *oc,= void *data) mc->desc =3D "ARM RealView Platform Baseboard Explore for Cortex-A9"; mc->init =3D realview_pbx_a9_init; mc->max_cpus =3D 4; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo realview_pbx_a9_type =3D { diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 4e7ac8c..ee140e5 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -122,6 +122,7 @@ static void sabrelite_machine_init(MachineClass *mc) mc->desc =3D "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)"; mc->init =3D sabrelite_init; mc->max_cpus =3D FSL_IMX6_NUM_CPUS; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("sabrelite", sabrelite_machine_init) diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 7f588ce..6406421 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -983,6 +983,7 @@ static void akitapda_class_init(ObjectClass *oc, void *= data) =20 mc->desc =3D "Sharp SL-C1000 (Akita) PDA (PXA270)"; mc->init =3D akita_init; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo akitapda_type =3D { @@ -998,6 +999,7 @@ static void spitzpda_class_init(ObjectClass *oc, void *= data) mc->desc =3D "Sharp SL-C3000 (Spitz) PDA (PXA270)"; mc->init =3D spitz_init; mc->block_default_type =3D IF_IDE; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo spitzpda_type =3D { @@ -1013,6 +1015,7 @@ static void borzoipda_class_init(ObjectClass *oc, voi= d *data) mc->desc =3D "Sharp SL-C3100 (Borzoi) PDA (PXA270)"; mc->init =3D borzoi_init; mc->block_default_type =3D IF_IDE; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo borzoipda_type =3D { @@ -1028,6 +1031,7 @@ static void terrierpda_class_init(ObjectClass *oc, vo= id *data) mc->desc =3D "Sharp SL-C3200 (Terrier) PDA (PXA270)"; mc->init =3D terrier_init; mc->block_default_type =3D IF_IDE; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo terrierpda_type =3D { diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 408c1a1..b3aad23 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1453,6 +1453,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, vo= id *data) =20 mc->desc =3D "Stellaris LM3S811EVB"; mc->init =3D lm3s811evb_init; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo lm3s811evb_type =3D { @@ -1467,6 +1468,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, v= oid *data) =20 mc->desc =3D "Stellaris LM3S6965EVB"; mc->init =3D lm3s6965evb_init; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo lm3s6965evb_type =3D { diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c index 8b757ff..1134cf7 100644 --- a/hw/arm/tosa.c +++ b/hw/arm/tosa.c @@ -263,6 +263,7 @@ static void tosapda_machine_init(MachineClass *mc) mc->desc =3D "Sharp SL-6000 (Tosa) PDA (PXA255)"; mc->init =3D tosa_init; mc->block_default_type =3D IF_IDE; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("tosa", tosapda_machine_init) diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index b0e9f5b..76664e4 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -403,6 +403,7 @@ static void versatilepb_class_init(ObjectClass *oc, voi= d *data) mc->desc =3D "ARM Versatile/PB (ARM926EJ-S)"; mc->init =3D vpb_init; mc->block_default_type =3D IF_SCSI; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo versatilepb_type =3D { @@ -418,6 +419,7 @@ static void versatileab_class_init(ObjectClass *oc, voi= d *data) mc->desc =3D "ARM Versatile/AB (ARM926EJ-S)"; mc->init =3D vab_init; mc->block_default_type =3D IF_SCSI; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo versatileab_type =3D { diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 571dd36..e3acab6 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -752,6 +752,7 @@ static void vexpress_class_init(ObjectClass *oc, void *= data) mc->desc =3D "ARM Versatile Express"; mc->init =3D vexpress_common_init; mc->max_cpus =3D 4; + mc->ignore_memory_transaction_failures =3D true; } =20 static void vexpress_a9_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index a750959..3759cf8 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -326,6 +326,7 @@ static void zynq_machine_init(MachineClass *mc) mc->init =3D zynq_init; mc->max_cpus =3D 1; mc->no_sdcard =3D 1; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c index 860780a..c339cd4 100644 --- a/hw/arm/xlnx-ep108.c +++ b/hw/arm/xlnx-ep108.c @@ -122,6 +122,7 @@ static void xlnx_ep108_machine_init(MachineClass *mc) mc->init =3D xlnx_ep108_init; mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init) @@ -132,6 +133,7 @@ static void xlnx_zcu102_machine_init(MachineClass *mc) mc->init =3D xlnx_ep108_init; mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("xlnx-zcu102", xlnx_zcu102_machine_init) diff --git a/hw/arm/z2.c b/hw/arm/z2.c index 1607cbd..417bc1a 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -370,6 +370,7 @@ static void z2_machine_init(MachineClass *mc) { mc->desc =3D "Zipit Z2 (PXA27x)"; mc->init =3D z2_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("z2", z2_machine_init) --=20 2.7.4 From nobody Sun May 5 03:23:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 05 Sep 2017 11:53:29 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dpGA9-00079o-NJ; Tue, 05 Sep 2017 16:53:17 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 5 Sep 2017 16:53:34 +0100 Message-Id: <1504626814-23124-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1504626814-23124-1-git-send-email-peter.maydell@linaro.org> References: <1504626814-23124-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH v2 3/3] target/arm: Implement new do_transaction_failed hook X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement the new do_transaction_failed hook for ARM, which should cause the CPU to take a prefetch abort or data abort. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Edgar E. Iglesias --- target/arm/internals.h | 10 ++++++++++ target/arm/cpu.c | 1 + target/arm/op_helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index 461f558..b100da9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -472,6 +472,16 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr v= addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); =20 +/* arm_cpu_do_transaction_failed: handle a memory system error response + * (eg "no device/memory present at address") by raising an external abort + * exception + */ +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr= ); + /* Call the EL change hook if one has been registered */ static inline void arm_call_el_change_hook(ARMCPU *cpu) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 41ae6ba..a323e6b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1667,6 +1667,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #else cc->do_interrupt =3D arm_cpu_do_interrupt; cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; + cc->do_transaction_failed =3D arm_cpu_do_transaction_failed; cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->vmsd =3D &vmstate_arm_cpu; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 8f6db80..d1bca46 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -229,6 +229,49 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr v= addr, deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi); } =20 +/* arm_cpu_do_transaction_failed: handle a memory system error response + * (eg "no device/memory present at address") by raising an external abort + * exception + */ +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint32_t fsr, fsc; + ARMMMUFaultInfo fi =3D {}; + ARMMMUIdx arm_mmu_idx =3D core_to_arm_mmu_idx(env, mmu_idx); + + if (retaddr) { + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); + } + + /* The EA bit in syndromes and fault status registers is an + * IMPDEF classification of external aborts. ARM implementations + * usually use this to indicate AXI bus Decode error (0) or + * Slave error (1); in QEMU we follow that. + */ + fi.ea =3D (response !=3D MEMTX_DECODE_ERROR); + + /* The fault status register format depends on whether we're using + * the LPAE long descriptor format, or the short descriptor format. + */ + if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { + /* long descriptor form, STATUS 0b010000: synchronous ext abort */ + fsr =3D (fi.ea << 12) | (1 << 9) | 0x10; + } else { + /* short descriptor form, FSR 0b01000 : synchronous ext abort */ + fsr =3D (fi.ea << 12) | 0x8; + } + fsc =3D 0x10; + + deliver_fault(cpu, addr, access_type, fsr, fsc, &fi); +} + #endif /* !defined(CONFIG_USER_ONLY) */ =20 uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) --=20 2.7.4