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X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/36] target/arm: Create and use new function arm_v7m_is_handler_mode() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+famz=redhat.com@nongnu.org Sender: "Qemu-devel" X-Greylist: Sender passed SPF test, Sender IP whitelisted by DNSRBL, ACL 205 matched, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Mon, 04 Sep 2017 12:39:08 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Mon, 04 Sep 2017 12:39:08 +0000 (UTC) for IP:'208.118.235.17' DOMAIN:'lists.gnu.org' HELO:'lists.gnu.org' FROM:'redhat.com@nongnu.org' RCPT:'' X-RedHat-Spam-Score: -5.02 (HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_HI,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_PASS) 208.118.235.17 lists.gnu.org 208.118.235.17 lists.gnu.org X-Scanned-By: MIMEDefang 2.78 on 10.5.110.26 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Content-Length: 3579 Add a utility function for testing whether the CPU is in Handler mode; this is just a check whether v7m.exception is non-zero, but we do it in several places and it makes the code a bit easier to read to not have to mentally figure out what the test is testing. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson Message-id: 1501692241-23310-14-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 10 ++++++++-- target/arm/helper.c | 8 ++++---- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8ef552a..eabef00 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1629,13 +1629,19 @@ static inline int arm_highest_el(CPUARMState *env) return 1; } =20 +/* Return true if a v7M CPU is in Handler mode */ +static inline bool arm_v7m_is_handler_mode(CPUARMState *env) +{ + return env->v7m.exception !=3D 0; +} + /* Return the current Exception Level (as per ARMv8; note that this differs * from the ARMv7 Privilege Level). */ static inline int arm_current_el(CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_M)) { - return !((env->v7m.exception =3D=3D 0) && (env->v7m.control & 1)); + return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1); } =20 if (is_a64(env)) { @@ -2635,7 +2641,7 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *= env, target_ulong *pc, } *flags |=3D fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; =20 - if (env->v7m.exception !=3D 0) { + if (arm_v7m_is_handler_mode(env)) { *flags |=3D ARM_TBFLAG_HANDLER_MASK; } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 267a170..37e7fd9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6142,7 +6142,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * that jumps to magic addresses don't have magic behaviour unless * we're in Handler mode (compare pseudocode BXWritePC()). */ - assert(env->v7m.exception !=3D 0); + assert(arm_v7m_is_handler_mode(env)); =20 /* In the spec pseudocode ExceptionReturn() is called directly * from BXWritePC() and gets the full target PC value including @@ -6249,7 +6249,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * resuming in Thread mode. If that doesn't match what the * exception return type specified then this is a UsageFault. */ - if (return_to_handler =3D=3D (env->v7m.exception =3D=3D 0)) { + if (return_to_handler !=3D arm_v7m_is_handler_mode(env)) { /* Take an INVPC UsageFault by pushing the stack again. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); env->v7m.cfsr |=3D R_V7M_CFSR_INVPC_MASK; @@ -6400,7 +6400,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { lr |=3D 4; } - if (env->v7m.exception =3D=3D 0) { + if (!arm_v7m_is_handler_mode(env)) { lr |=3D 8; } =20 @@ -8793,7 +8793,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) * switch_v7m_sp() deals with updating the SPSEL bit in * env->v7m.control, so we only need update the others. */ - if (env->v7m.exception =3D=3D 0) { + if (!arm_v7m_is_handler_mode(env)) { switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) !=3D 0); } env->v7m.control &=3D ~R_V7M_CONTROL_NPRIV_MASK; --=20 2.7.4