From nobody Wed Apr 9 00:54:10 2025 Return-Path: qemu-devel-bounces+famz=redhat.com@nongnu.org Received: from zmta02.collab.prod.int.phx2.redhat.com (LHLO zmta02.collab.prod.int.phx2.redhat.com) (10.5.81.9) by zmail26.collab.prod.int.phx2.redhat.com with LMTP; Mon, 4 Sep 2017 08:32:50 -0400 (EDT) Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) by zmta02.collab.prod.int.phx2.redhat.com (Postfix) with ESMTP id 6C28C122F96 for ; Mon, 4 Sep 2017 08:32:50 -0400 (EDT) Received: by smtp.corp.redhat.com (Postfix) id 61A99C0DA8; Mon, 4 Sep 2017 12:32:50 +0000 (UTC) Delivered-To: famz@redhat.com Received: from mx1.redhat.com (ext-mx05.extmail.prod.ext.phx2.redhat.com [10.5.110.29]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 46CD2116D68 for ; Mon, 4 Sep 2017 12:32:42 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 46A872C96C6 for ; Mon, 4 Sep 2017 12:32:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 46A872C96C6 Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: ext-mx05.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=qemu-devel-bounces+famz=redhat.com@nongnu.org DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 46A872C96C6 Received: from localhost ([::1]:59558 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1doqYS-0000Sh-F6 for famz@redhat.com; Mon, 04 Sep 2017 08:32:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52383) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1doqSI-0004tp-50 for qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1doqS7-0004he-4m for qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:18 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37110) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1doqS6-0004ej-Tm for qemu-devel@nongnu.org; Mon, 04 Sep 2017 08:26:07 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1doqS5-0005Ts-RL for qemu-devel@nongnu.org; Mon, 04 Sep 2017 13:26:05 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 4 Sep 2017 13:25:42 +0100 Message-Id: <1504527967-29248-12-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1504527967-29248-1-git-send-email-peter.maydell@linaro.org> References: <1504527967-29248-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 11/36] target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+famz=redhat.com@nongnu.org Sender: "Qemu-devel" X-Greylist: Sender passed SPF test, Sender IP whitelisted by DNSRBL, ACL 205 matched, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Mon, 04 Sep 2017 12:32:41 +0000 (UTC) X-Greylist: inspected by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Mon, 04 Sep 2017 12:32:41 +0000 (UTC) for IP:'208.118.235.17' DOMAIN:'lists.gnu.org' HELO:'lists.gnu.org' FROM:'redhat.com@nongnu.org' RCPT:'' X-RedHat-Spam-Score: -5.02 (HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_HI,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_PASS) 208.118.235.17 lists.gnu.org 208.118.235.17 lists.gnu.org X-Scanned-By: MIMEDefang 2.78 on 10.5.110.29 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 Content-Length: 3365 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the arm_cpu_dump_state() debug logging handle the M-profile XPSR rather than assuming it's an A-profile CPSR. On M profile the PSR line of a register dump will now look like this: XPSR=3D41000000 -Z-- T priv-thread Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson Message-id: 1501692241-23310-12-git-send-email-peter.maydell@linaro.org --- target/arm/translate.c | 58 ++++++++++++++++++++++++++++++++++------------= ---- 1 file changed, 40 insertions(+), 18 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 3c14cb0..e52a6d7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12215,8 +12215,6 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fpri= ntf_function cpu_fprintf, ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; int i; - uint32_t psr; - const char *ns_status; =20 if (is_a64(env)) { aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags); @@ -12230,24 +12228,48 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fp= rintf_function cpu_fprintf, else cpu_fprintf(f, " "); } - psr =3D cpsr_read(env); =20 - if (arm_feature(env, ARM_FEATURE_EL3) && - (psr & CPSR_M) !=3D ARM_CPU_MODE_MON) { - ns_status =3D env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + if (arm_feature(env, ARM_FEATURE_M)) { + uint32_t xpsr =3D xpsr_read(env); + const char *mode; + + if (xpsr & XPSR_EXCP) { + mode =3D "handler"; + } else { + if (env->v7m.control & R_V7M_CONTROL_NPRIV_MASK) { + mode =3D "unpriv-thread"; + } else { + mode =3D "priv-thread"; + } + } + + cpu_fprintf(f, "XPSR=3D%08x %c%c%c%c %c %s\n", + xpsr, + xpsr & XPSR_N ? 'N' : '-', + xpsr & XPSR_Z ? 'Z' : '-', + xpsr & XPSR_C ? 'C' : '-', + xpsr & XPSR_V ? 'V' : '-', + xpsr & XPSR_T ? 'T' : 'A', + mode); } else { - ns_status =3D ""; - } - - cpu_fprintf(f, "PSR=3D%08x %c%c%c%c %c %s%s%d\n", - psr, - psr & (1 << 31) ? 'N' : '-', - psr & (1 << 30) ? 'Z' : '-', - psr & (1 << 29) ? 'C' : '-', - psr & (1 << 28) ? 'V' : '-', - psr & CPSR_T ? 'T' : 'A', - ns_status, - cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); + uint32_t psr =3D cpsr_read(env); + const char *ns_status =3D ""; + + if (arm_feature(env, ARM_FEATURE_EL3) && + (psr & CPSR_M) !=3D ARM_CPU_MODE_MON) { + ns_status =3D env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + } + + cpu_fprintf(f, "PSR=3D%08x %c%c%c%c %c %s%s%d\n", + psr, + psr & CPSR_N ? 'N' : '-', + psr & CPSR_Z ? 'Z' : '-', + psr & CPSR_C ? 'C' : '-', + psr & CPSR_V ? 'V' : '-', + psr & CPSR_T ? 'T' : 'A', + ns_status, + cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); + } =20 if (flags & CPU_DUMP_FPU) { int numvfpregs =3D 0; --=20 2.7.4