From nobody Mon Feb 9 00:30:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503938426122272.98906272920124; Mon, 28 Aug 2017 09:40:26 -0700 (PDT) Received: from localhost ([::1]:40612 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmN5L-0003Fh-V4 for importer@patchew.org; Mon, 28 Aug 2017 12:40:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45168) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dmN3R-0001xb-Ds for qemu-devel@nongnu.org; Mon, 28 Aug 2017 12:38:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dmN3P-00039K-H1 for qemu-devel@nongnu.org; Mon, 28 Aug 2017 12:38:25 -0400 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:35399) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dmN3P-00035t-8N; Mon, 28 Aug 2017 12:38:23 -0400 Received: by mail-pf0-x243.google.com with SMTP id g13so639906pfm.2; Mon, 28 Aug 2017 09:38:23 -0700 (PDT) Received: from localhost.localdomain ([124.123.70.3]) by smtp.gmail.com with ESMTPSA id n66sm1935015pfi.44.2017.08.28.09.38.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 28 Aug 2017 09:38:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BQAgqzIMWsJa3UCJkaq93RV6GILFbBbQfxQBdsI78B0=; b=CXW0FBZ6NVdhp4q4Uwdk+n/IofJnByK2bgtsH896G51nkwXj+8oednGPEYODnCiHdk EpUg2LLqG89cqiGNf8qyrXcH6fo4+f+gTbhpoTMlgeaja3JbWuQdNPm+xzplwKnhOIdT I41bQdlTWMb/lnFmbAzfnmwKpMDWu+tnruqlZpdB94RmeCNx3u39APqS0dNQlRFYQTCj NuE2t+315Flsg5C1dtRbC+PNM1+ouK4JNQUOIrGZ788b+j3BTj3MYcmODJnKe1+H0N0z V7vsqd5Bnbc/kPxkFf785TjqlR9uwFMSgw/9n/0CFEPaQJGZGCI6qDtxdZyqZ0l8jxr9 pRLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BQAgqzIMWsJa3UCJkaq93RV6GILFbBbQfxQBdsI78B0=; b=eV2+4y3I24ZStURMVXQMHJ87IehY0/ljqfWunxApKJLvwnTUeofdQeOywTwKLK93e0 d6WexjBH9IJcsniekPP4C8HZxWSGNIy0n/REpSYXp3/j2HX+xLNvu2APA0k/1uEuqYxy v9S6xdeWLAZh/Wt4ToFxMWwsHtK28cl5UfcE6FymuqafoWbP1Q9EzX4sYBo/Ta+4DNca tcfh/grkYoZDFSZ6rF45og5jFML5CJFn6BzBkh+mU6rS7dwfnEr/1V1qNC5aAFLTjkXN tonCHqsC3aknWBKEyNw9/v2X9wm7BC8gsRq1S7Vr/APexMxhlnzQq8CbFjGQt28/Z4FS pJAA== X-Gm-Message-State: AHYfb5joMJ1qi/2kDxqlJHUnZWvUmU8T7YRraADNqx1Vv9yoIgkS55Uf KkB2MP5m3B6ZB+p/ X-Google-Smtp-Source: ADKCNb4vl0bVTTSfJ71wvmOaNPGwjYVWwcos+CRt6v/GaOtPeV2SJseWkG8RC/+Op33lzugxjvQ/3g== X-Received: by 10.84.129.47 with SMTP id 44mr1480087plb.40.1503938302107; Mon, 28 Aug 2017 09:38:22 -0700 (PDT) From: Subbaraya Sundeep To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Mon, 28 Aug 2017 22:08:00 +0530 Message-Id: <1503938283-12404-3-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.5.0 In-Reply-To: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> References: <1503938283-12404-1-git-send-email-sundeep.lkml@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [Qemu devel v7 PATCH 2/5] msf2: Microsemi Smartfusion2 System Register block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Subbaraya Sundeep , f4bug@amsat.org, alistair23@gmail.com, crosthwaite.peter@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Added Sytem register block of Smartfusion2. This block has PLL registers which are accessed by guest. Signed-off-by: Subbaraya Sundeep Reviewed-by: Alistair Francis --- hw/misc/Makefile.objs | 1 + hw/misc/msf2-sysreg.c | 199 ++++++++++++++++++++++++++++++++++++++= ++++ include/hw/misc/msf2-sysreg.h | 78 +++++++++++++++++ 3 files changed, 278 insertions(+) create mode 100644 hw/misc/msf2-sysreg.c create mode 100644 include/hw/misc/msf2-sysreg.h diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 29fb922..e8f0a02 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -59,3 +59,4 @@ obj-$(CONFIG_HYPERV_TESTDEV) +=3D hyperv_testdev.o obj-$(CONFIG_AUX) +=3D auxbus.o obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_scu.o aspeed_sdmc.o obj-y +=3D mmio_interface.o +obj-$(CONFIG_MSF2) +=3D msf2-sysreg.o diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c new file mode 100644 index 0000000..2aeb555 --- /dev/null +++ b/hw/misc/msf2-sysreg.c @@ -0,0 +1,199 @@ +/* + * System Register block model of Microsemi SmartFusion2. + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/misc/msf2-sysreg.h" + +#ifndef MSF2_SYSREG_ERR_DEBUG +#define MSF2_SYSREG_ERR_DEBUG 0 +#endif + +#define DB_PRINT_L(lvl, fmt, args...) do { \ + if (MSF2_SYSREG_ERR_DEBUG >=3D lvl) { \ + qemu_log("%s: " fmt "\n", __func__, ## args); \ + } \ +} while (0); + +#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) + +static inline int msf2_divbits(uint32_t div) +{ + int ret =3D 0; + + switch (div) { + case 1: + ret =3D 0; + break; + case 2: + ret =3D 1; + break; + case 4: + ret =3D 2; + break; + case 8: + ret =3D 4; + break; + case 16: + ret =3D 5; + break; + case 32: + ret =3D 6; + break; + default: + break; + } + + return ret; +} + +static void msf2_sysreg_reset(DeviceState *d) +{ + MSF2SysregState *s =3D MSF2_SYSREG(d); + + DB_PRINT("RESET"); + + s->regs[MSSDDR_PLL_STATUS_LOW_CR] =3D 0x021A2358; + s->regs[MSSDDR_PLL_STATUS] =3D 0x3; + s->regs[MSSDDR_FACC1_CR] =3D msf2_divbits(s->apb0div) << 5 | + msf2_divbits(s->apb1div) << 2; +} + +static uint64_t msf2_sysreg_read(void *opaque, hwaddr offset, + unsigned size) +{ + MSF2SysregState *s =3D opaque; + uint32_t ret =3D 0; + + offset >>=3D 2; + if (offset < ARRAY_SIZE(s->regs)) { + ret =3D s->regs[offset]; + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx32, + offset << 2, ret); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__, + offset << 2); + } + + return ret; +} + +static void msf2_sysreg_write(void *opaque, hwaddr offset, + uint64_t val, unsigned size) +{ + MSF2SysregState *s =3D (MSF2SysregState *)opaque; + uint32_t newval =3D val; + uint32_t oldval; + + DB_PRINT("addr: 0x%08" HWADDR_PRIx " data: 0x%08" PRIx64, + offset, val); + + offset >>=3D 2; + + switch (offset) { + case MSSDDR_PLL_STATUS: + break; + + case ESRAM_CR: + oldval =3D s->regs[ESRAM_CR]; + if (oldval ^ newval) { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSF2_SYSREG": eSRAM remapping not supported\n"= ); + } + break; + + case DDR_CR: + oldval =3D s->regs[DDR_CR]; + if (oldval ^ newval) { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSF2_SYSREG": DDR remapping not supported\n"); + } + break; + + case ENVM_REMAP_BASE_CR: + oldval =3D s->regs[ENVM_REMAP_BASE_CR]; + if (oldval ^ newval) { + qemu_log_mask(LOG_GUEST_ERROR, + TYPE_MSF2_SYSREG": eNVM remapping not supported\n"); + } + break; + + default: + if (offset < ARRAY_SIZE(s->regs)) { + s->regs[offset] =3D val; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%08" HWADDR_PRIx "\n", __func__, + offset << 2); + } + break; + } +} + +static const MemoryRegionOps sysreg_ops =3D { + .read =3D msf2_sysreg_read, + .write =3D msf2_sysreg_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + +static void msf2_sysreg_init(Object *obj) +{ + MSF2SysregState *s =3D MSF2_SYSREG(obj); + + memory_region_init_io(&s->iomem, obj, &sysreg_ops, s, TYPE_MSF2_SYSREG, + MSF2_SYSREG_MMIO_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); +} + +static const VMStateDescription vmstate_msf2_sysreg =3D { + .name =3D TYPE_MSF2_SYSREG, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, MSF2SysregState, MSF2_SYSREG_MMIO_SIZE = / 4), + VMSTATE_END_OF_LIST() + } +}; + +static Property msf2_sysreg_properties[] =3D { + /* default divisors in Libero GUI */ + DEFINE_PROP_UINT32("apb0divisor", MSF2SysregState, apb0div, 2), + DEFINE_PROP_UINT32("apb1divisor", MSF2SysregState, apb1div, 2), + DEFINE_PROP_END_OF_LIST(), +}; + +static void msf2_sysreg_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_msf2_sysreg; + dc->reset =3D msf2_sysreg_reset; + dc->props =3D msf2_sysreg_properties; +} + +static const TypeInfo msf2_sysreg_info =3D { + .name =3D TYPE_MSF2_SYSREG, + .parent =3D TYPE_SYS_BUS_DEVICE, + .class_init =3D msf2_sysreg_class_init, + .instance_size =3D sizeof(MSF2SysregState), + .instance_init =3D msf2_sysreg_init, +}; + +static void msf2_sysreg_register_types(void) +{ + type_register_static(&msf2_sysreg_info); +} + +type_init(msf2_sysreg_register_types) diff --git a/include/hw/misc/msf2-sysreg.h b/include/hw/misc/msf2-sysreg.h new file mode 100644 index 0000000..f39cc41 --- /dev/null +++ b/include/hw/misc/msf2-sysreg.h @@ -0,0 +1,78 @@ +/* + * Microsemi SmartFusion2 SYSREG + * + * Copyright (c) 2017 Subbaraya Sundeep + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_MSF2_SYSREG_H +#define HW_MSF2_SYSREG_H + +#include "hw/sysbus.h" + +enum { + ESRAM_CR =3D 0x00 / 4, + ESRAM_MAX_LAT, + DDR_CR, + ENVM_CR, + ENVM_REMAP_BASE_CR, + ENVM_REMAP_FAB_CR, + CC_CR, + CC_REGION_CR, + CC_LOCK_BASE_ADDR_CR, + CC_FLUSH_INDX_CR, + DDRB_BUF_TIMER_CR, + DDRB_NB_ADDR_CR, + DDRB_NB_SIZE_CR, + DDRB_CR, + + SOFT_RESET_CR =3D 0x48 / 4, + M3_CR, + + GPIO_SYSRESET_SEL_CR =3D 0x58 / 4, + + MDDR_CR =3D 0x60 / 4, + + MSSDDR_PLL_STATUS_LOW_CR =3D 0x90 / 4, + MSSDDR_PLL_STATUS_HIGH_CR, + MSSDDR_FACC1_CR, + MSSDDR_FACC2_CR, + + MSSDDR_PLL_STATUS =3D 0x150 / 4, + +}; + +#define MSF2_SYSREG_MMIO_SIZE 0x300 + +#define TYPE_MSF2_SYSREG "msf2-sysreg" +#define MSF2_SYSREG(obj) OBJECT_CHECK(MSF2SysregState, (obj), TYPE_MSF2_S= YSREG) + +typedef struct MSF2SysregState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + uint32_t apb0div; + uint32_t apb1div; + + uint32_t regs[MSF2_SYSREG_MMIO_SIZE / 4]; +} MSF2SysregState; + +#endif /* HW_MSF2_SYSREG_H */ --=20 2.5.0