From nobody Mon Feb 9 14:37:44 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503416980379578.1398963551464; Tue, 22 Aug 2017 08:49:40 -0700 (PDT) Received: from localhost ([::1]:56341 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBQw-0000mv-U6 for importer@patchew.org; Tue, 22 Aug 2017 11:49:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53439) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnr-0006Vl-3a for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAno-0003ES-Ac for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:15 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36966) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnk-00039F-2M; Tue, 22 Aug 2017 11:09:08 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnj-0004j5-52; Tue, 22 Aug 2017 16:09:07 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:52 +0100 Message-Id: <1503414539-28762-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 13/20] target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled. We can freely add more items to vmstate_m_security without breaking migration compatibility, because no CPU currently has the ARM_FEATURE_M_SECURITY bit enabled and so this subsection is not yet used by anything. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- hw/intc/armv7m_nvic.c | 8 ++++---- target/arm/cpu.c | 26 ++++++++++++++++++++------ target/arm/helper.c | 11 ++++++----- target/arm/machine.c | 12 ++++++++---- 5 files changed, 40 insertions(+), 21 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2f59828..12fa95e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -543,8 +543,8 @@ typedef struct CPUARMState { * pmsav7.rnr (region number register) * pmsav7_dregion (number of configured regions) */ - uint32_t *rbar; - uint32_t *rlar; + uint32_t *rbar[2]; + uint32_t *rlar[2]; uint32_t mair0[2]; uint32_t mair1[2]; } pmsav8; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index e98eb95..9ced7af 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -564,7 +564,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t, MemTxAttrs attrs) if (region >=3D cpu->pmsav7_dregion) { return 0; } - return cpu->env.pmsav8.rbar[region]; + return cpu->env.pmsav8.rbar[attrs.secure][region]; } =20 if (region >=3D cpu->pmsav7_dregion) { @@ -591,7 +591,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t, MemTxAttrs attrs) if (region >=3D cpu->pmsav7_dregion) { return 0; } - return cpu->env.pmsav8.rlar[region]; + return cpu->env.pmsav8.rlar[attrs.secure][region]; } =20 if (region >=3D cpu->pmsav7_dregion) { @@ -756,7 +756,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value, if (region >=3D cpu->pmsav7_dregion) { return; } - cpu->env.pmsav8.rbar[region] =3D value; + cpu->env.pmsav8.rbar[attrs.secure][region] =3D value; tlb_flush(CPU(cpu)); return; } @@ -806,7 +806,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value, if (region >=3D cpu->pmsav7_dregion) { return; } - cpu->env.pmsav8.rlar[region] =3D value; + cpu->env.pmsav8.rlar[attrs.secure][region] =3D value; tlb_flush(CPU(cpu)); return; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ae8af19..333029c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -235,10 +235,20 @@ static void arm_cpu_reset(CPUState *s) if (arm_feature(env, ARM_FEATURE_PMSA)) { if (cpu->pmsav7_dregion > 0) { if (arm_feature(env, ARM_FEATURE_V8)) { - memset(env->pmsav8.rbar, 0, - sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion); - memset(env->pmsav8.rlar, 0, - sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion); + memset(env->pmsav8.rbar[M_REG_NS], 0, + sizeof(*env->pmsav8.rbar[M_REG_NS]) + * cpu->pmsav7_dregion); + memset(env->pmsav8.rlar[M_REG_NS], 0, + sizeof(*env->pmsav8.rlar[M_REG_NS]) + * cpu->pmsav7_dregion); + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + memset(env->pmsav8.rbar[M_REG_S], 0, + sizeof(*env->pmsav8.rbar[M_REG_S]) + * cpu->pmsav7_dregion); + memset(env->pmsav8.rlar[M_REG_S], 0, + sizeof(*env->pmsav8.rlar[M_REG_S]) + * cpu->pmsav7_dregion); + } } else if (arm_feature(env, ARM_FEATURE_V7)) { memset(env->pmsav7.drbar, 0, sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); @@ -823,8 +833,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) if (nr) { if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ - env->pmsav8.rbar =3D g_new0(uint32_t, nr); - env->pmsav8.rlar =3D g_new0(uint32_t, nr); + env->pmsav8.rbar[M_REG_NS] =3D g_new0(uint32_t, nr); + env->pmsav8.rlar[M_REG_NS] =3D g_new0(uint32_t, nr); + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + env->pmsav8.rbar[M_REG_S] =3D g_new0(uint32_t, nr); + env->pmsav8.rlar[M_REG_S] =3D g_new0(uint32_t, nr); + } } else { env->pmsav7.drbar =3D g_new0(uint32_t, nr); env->pmsav7.drsr =3D g_new0(uint32_t, nr); diff --git a/target/arm/helper.c b/target/arm/helper.c index b1bb507..5394cef 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8442,6 +8442,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, { ARMCPU *cpu =3D arm_env_get_cpu(env); bool is_user =3D regime_is_user(env, mmu_idx); + uint32_t secure =3D regime_is_secure(env, mmu_idx); int n; int matchregion =3D -1; bool hit =3D false; @@ -8468,10 +8469,10 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, = uint32_t address, * with bits [4:0] all zeroes, but the limit address is bits * [31:5] from the register with bits [4:0] all ones. */ - uint32_t base =3D env->pmsav8.rbar[n] & ~0x1f; - uint32_t limit =3D env->pmsav8.rlar[n] | 0x1f; + uint32_t base =3D env->pmsav8.rbar[secure][n] & ~0x1f; + uint32_t limit =3D env->pmsav8.rlar[secure][n] | 0x1f; =20 - if (!(env->pmsav8.rlar[n] & 0x1)) { + if (!(env->pmsav8.rlar[secure][n] & 0x1)) { /* Region disabled */ continue; } @@ -8520,8 +8521,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, /* hit using the background region */ get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); } else { - uint32_t ap =3D extract32(env->pmsav8.rbar[matchregion], 1, 2); - uint32_t xn =3D extract32(env->pmsav8.rbar[matchregion], 0, 1); + uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); + uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); =20 if (m_is_system_region(env, address)) { /* System space is always execute never */ diff --git a/target/arm/machine.c b/target/arm/machine.c index 414a879..05c6c7a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -225,10 +225,10 @@ static const VMStateDescription vmstate_pmsav8 =3D { .minimum_version_id =3D 1, .needed =3D pmsav8_needed, .fields =3D (VMStateField[]) { - VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0, - vmstate_info_uint32, uint32_t), - VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, - vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dr= egion, + 0, vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dr= egion, + 0, vmstate_info_uint32, uint32_t), VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() @@ -257,6 +257,10 @@ static const VMStateDescription vmstate_m_security =3D= { VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dre= gion, + 0, vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dre= gion, + 0, vmstate_info_uint32, uint32_t), VMSTATE_END_OF_LIST() } }; --=20 2.7.4