From nobody Mon Feb 9 14:37:44 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503415547134812.64476335497; Tue, 22 Aug 2017 08:25:47 -0700 (PDT) Received: from localhost ([::1]:54011 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkB3p-0003dK-I7 for importer@patchew.org; Tue, 22 Aug 2017 11:25:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53543) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnv-0006cy-Pi for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAns-0003J4-CI for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:19 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAni-00037y-Gd; Tue, 22 Aug 2017 11:09:06 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnh-0004i6-H2; Tue, 22 Aug 2017 16:09:05 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:50 +0100 Message-Id: <1503414539-28762-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 11/20] target/arm: Make VTOR register banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the VTOR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 13 +++++++------ target/arm/helper.c | 2 +- target/arm/machine.c | 3 ++- 4 files changed, 11 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e922d1f..d0b0936 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -420,7 +420,7 @@ typedef struct CPUARMState { =20 struct { uint32_t other_sp; - uint32_t vecbase; + uint32_t vecbase[2]; uint32_t basepri[2]; uint32_t control[2]; uint32_t ccr; /* Configuration and Control */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2b0b328..3a1f02d 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -403,7 +403,7 @@ static void set_irq_level(void *opaque, int n, int leve= l) } } =20 -static uint32_t nvic_readl(NVICState *s, uint32_t offset) +static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) { ARMCPU *cpu =3D s->cpu; uint32_t val; @@ -441,7 +441,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t) /* ISRPREEMPT not implemented */ return val; case 0xd08: /* Vector Table Offset. */ - return cpu->env.v7m.vecbase; + return cpu->env.v7m.vecbase[attrs.secure]; case 0xd0c: /* Application Interrupt/Reset Control. */ return 0xfa050000 | (s->prigroup << 8); case 0xd10: /* System Control. */ @@ -617,7 +617,8 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t) } } =20 -static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) +static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, + MemTxAttrs attrs) { ARMCPU *cpu =3D s->cpu; =20 @@ -638,7 +639,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value) } break; case 0xd08: /* Vector Table Offset. */ - cpu->env.v7m.vecbase =3D value & 0xffffff80; + cpu->env.v7m.vecbase[attrs.secure] =3D value & 0xffffff80; break; case 0xd0c: /* Application Interrupt/Reset Control. */ if ((value >> 16) =3D=3D 0x05fa) { @@ -944,7 +945,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwadd= r addr, break; default: if (size =3D=3D 4) { - val =3D nvic_readl(s, offset); + val =3D nvic_readl(s, offset, attrs); } else { qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read of size %d at offset 0x%x\n", @@ -1025,7 +1026,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hw= addr addr, return MEMTX_OK; } if (size =3D=3D 4) { - nvic_writel(s, offset, value); + nvic_writel(s, offset, value, attrs); return MEMTX_OK; } qemu_log_mask(LOG_GUEST_ERROR, diff --git a/target/arm/helper.c b/target/arm/helper.c index 8e74b10..b1bb507 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6072,7 +6072,7 @@ static uint32_t arm_v7m_load_vector(ARMCPU *cpu) CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; MemTxResult result; - hwaddr vec =3D env->v7m.vecbase + env->v7m.exception * 4; + hwaddr vec =3D env->v7m.vecbase[env->v7m.secure] + env->v7m.exception = * 4; uint32_t addr; =20 addr =3D address_space_ldl(cs->as, vec, diff --git a/target/arm/machine.c b/target/arm/machine.c index 2cd64c5..cd6b6af 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -114,7 +114,7 @@ static const VMStateDescription vmstate_m =3D { .minimum_version_id =3D 4, .needed =3D m_needed, .fields =3D (VMStateField[]) { - VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), + VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.ccr, ARMCPU), @@ -254,6 +254,7 @@ static const VMStateDescription vmstate_m_security =3D { VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; --=20 2.7.4