From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15034179863871004.2629365903698; Tue, 22 Aug 2017 09:06:26 -0700 (PDT) Received: from localhost ([::1]:57731 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBhA-0006rr-Qv for importer@patchew.org; Tue, 22 Aug 2017 12:06:24 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53666) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnz-0006iZ-U9 for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnx-0003Mo-MO for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:23 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnm-00037y-IE; Tue, 22 Aug 2017 11:09:10 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnZ-0004dj-QG; Tue, 22 Aug 2017 16:08:57 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:40 +0100 Message-Id: <1503414539-28762-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 01/20] target/arm: Implement ARMv8M's PMSAv8 registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As part of ARMv8M, we need to add support for the PMSAv8 MPU architecture. PMSAv8 differs from PMSAv7 both in register/data layout (for instance using base and limit registers rather than base and size) and also in behaviour (for example it does not have subregions); rather than trying to wedge it into the existing PMSAv7 code and data structures, we define separate ones. This commit adds the data structures which hold the state for a PMSAv8 MPU and the register interface to it. The implementation of the MPU behaviour will be added in a subsequent commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 13 ++++++ hw/intc/armv7m_nvic.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++= ---- target/arm/cpu.c | 36 ++++++++++----- target/arm/machine.c | 28 +++++++++++- 4 files changed, 179 insertions(+), 20 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fe6edb7..b6bb78a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -522,6 +522,19 @@ typedef struct CPUARMState { uint32_t rnr; } pmsav7; =20 + /* PMSAv8 MPU */ + struct { + /* The PMSAv8 implementation also shares some PMSAv7 config + * and state: + * pmsav7.rnr (region number register) + * pmsav7_dregion (number of configured regions) + */ + uint32_t *rbar; + uint32_t *rlar; + uint32_t mair0; + uint32_t mair1; + } pmsav8; + void *nvic; const struct arm_boot_info *boot_info; /* Store GICv3CPUState to access from this struct */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index bbfe2d5..c0dbbad 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -544,25 +544,67 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set) { int region =3D cpu->env.pmsav7.rnr; =20 + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* PMSAv8M handling of the aliases is different from v7M: + * aliases A1, A2, A3 override the low two bits of the region + * number in MPU_RNR, and there is no 'region' field in the + * RBAR register. + */ + int aliasno =3D (offset - 0xd9c) / 8; /* 0..3 */ + if (aliasno) { + region =3D deposit32(region, 0, 2, aliasno); + } + if (region >=3D cpu->pmsav7_dregion) { + return 0; + } + return cpu->env.pmsav8.rbar[region]; + } + if (region >=3D cpu->pmsav7_dregion) { return 0; } return (cpu->env.pmsav7.drbar[region] & 0x1f) | (region & 0xf); } - case 0xda0: /* MPU_RASR */ - case 0xda8: /* MPU_RASR_A1 */ - case 0xdb0: /* MPU_RASR_A2 */ - case 0xdb8: /* MPU_RASR_A3 */ + case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ + case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ + case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ + case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ { int region =3D cpu->env.pmsav7.rnr; =20 + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* PMSAv8M handling of the aliases is different from v7M: + * aliases A1, A2, A3 override the low two bits of the region + * number in MPU_RNR. + */ + int aliasno =3D (offset - 0xda0) / 8; /* 0..3 */ + if (aliasno) { + region =3D deposit32(region, 0, 2, aliasno); + } + if (region >=3D cpu->pmsav7_dregion) { + return 0; + } + return cpu->env.pmsav8.rlar[region]; + } + if (region >=3D cpu->pmsav7_dregion) { return 0; } return ((cpu->env.pmsav7.dracr[region] & 0xffff) << 16) | (cpu->env.pmsav7.drsr[region] & 0xffff); } + case 0xdc0: /* MPU_MAIR0 */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + return cpu->env.pmsav8.mair0; + case 0xdc4: /* MPU_MAIR1 */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + return cpu->env.pmsav8.mair1; default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", off= set); return 0; } @@ -691,6 +733,26 @@ static void nvic_writel(NVICState *s, uint32_t offset,= uint32_t value) { int region; =20 + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* PMSAv8M handling of the aliases is different from v7M: + * aliases A1, A2, A3 override the low two bits of the region + * number in MPU_RNR, and there is no 'region' field in the + * RBAR register. + */ + int aliasno =3D (offset - 0xd9c) / 8; /* 0..3 */ + + region =3D cpu->env.pmsav7.rnr; + if (aliasno) { + region =3D deposit32(region, 0, 2, aliasno); + } + if (region >=3D cpu->pmsav7_dregion) { + return; + } + cpu->env.pmsav8.rbar[region] =3D value; + tlb_flush(CPU(cpu)); + return; + } + if (value & (1 << 4)) { /* VALID bit means use the region number specified in this * value and also update MPU_RNR.REGION with that value. @@ -715,13 +777,32 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value) tlb_flush(CPU(cpu)); break; } - case 0xda0: /* MPU_RASR */ - case 0xda8: /* MPU_RASR_A1 */ - case 0xdb0: /* MPU_RASR_A2 */ - case 0xdb8: /* MPU_RASR_A3 */ + case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */ + case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */ + case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ + case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ { int region =3D cpu->env.pmsav7.rnr; =20 + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* PMSAv8M handling of the aliases is different from v7M: + * aliases A1, A2, A3 override the low two bits of the region + * number in MPU_RNR. + */ + int aliasno =3D (offset - 0xd9c) / 8; /* 0..3 */ + + region =3D cpu->env.pmsav7.rnr; + if (aliasno) { + region =3D deposit32(region, 0, 2, aliasno); + } + if (region >=3D cpu->pmsav7_dregion) { + return; + } + cpu->env.pmsav8.rlar[region] =3D value; + tlb_flush(CPU(cpu)); + return; + } + if (region >=3D cpu->pmsav7_dregion) { return; } @@ -731,6 +812,30 @@ static void nvic_writel(NVICState *s, uint32_t offset,= uint32_t value) tlb_flush(CPU(cpu)); break; } + case 0xdc0: /* MPU_MAIR0 */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + if (cpu->pmsav7_dregion) { + /* Register is RES0 if no MPU regions are implemented */ + cpu->env.pmsav8.mair0 =3D value; + } + /* We don't need to do anything else because memory attributes + * only affect cacheability, and we don't implement caching. + */ + break; + case 0xdc4: /* MPU_MAIR1 */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + goto bad_offset; + } + if (cpu->pmsav7_dregion) { + /* Register is RES0 if no MPU regions are implemented */ + cpu->env.pmsav8.mair1 =3D value; + } + /* We don't need to do anything else because memory attributes + * only affect cacheability, and we don't implement caching. + */ + break; case 0xf00: /* Software Triggered Interrupt Register */ { int excnum =3D (value & 0x1ff) + NVIC_FIRST_IRQ; @@ -740,6 +845,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value) break; } default: + bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad write offset 0x%x\n", offset); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 41ae6ba..8b610de 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -228,17 +228,25 @@ static void arm_cpu_reset(CPUState *s) env->vfp.xregs[ARM_VFP_FPEXC] =3D 0; #endif =20 - if (arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V7)) { + if (arm_feature(env, ARM_FEATURE_PMSA)) { if (cpu->pmsav7_dregion > 0) { - memset(env->pmsav7.drbar, 0, - sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); - memset(env->pmsav7.drsr, 0, - sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); - memset(env->pmsav7.dracr, 0, - sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); + if (arm_feature(env, ARM_FEATURE_V8)) { + memset(env->pmsav8.rbar, 0, + sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion); + memset(env->pmsav8.rlar, 0, + sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion); + } else if (arm_feature(env, ARM_FEATURE_V7)) { + memset(env->pmsav7.drbar, 0, + sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); + memset(env->pmsav7.drsr, 0, + sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); + memset(env->pmsav7.dracr, 0, + sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); + } } env->pmsav7.rnr =3D 0; + env->pmsav8.mair0 =3D 0; + env->pmsav8.mair1 =3D 0; } =20 set_flush_to_zero(1, &env->vfp.standard_fp_status); @@ -809,9 +817,15 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) } =20 if (nr) { - env->pmsav7.drbar =3D g_new0(uint32_t, nr); - env->pmsav7.drsr =3D g_new0(uint32_t, nr); - env->pmsav7.dracr =3D g_new0(uint32_t, nr); + if (arm_feature(env, ARM_FEATURE_V8)) { + /* PMSAv8 */ + env->pmsav8.rbar =3D g_new0(uint32_t, nr); + env->pmsav8.rlar =3D g_new0(uint32_t, nr); + } else { + env->pmsav7.drbar =3D g_new0(uint32_t, nr); + env->pmsav7.drsr =3D g_new0(uint32_t, nr); + env->pmsav7.dracr =3D g_new0(uint32_t, nr); + } } } =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index 3193b00..05e2909 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -159,7 +159,8 @@ static bool pmsav7_needed(void *opaque) CPUARMState *env =3D &cpu->env; =20 return arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V7); + arm_feature(env, ARM_FEATURE_V7) && + !arm_feature(env, ARM_FEATURE_V8); } =20 static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) @@ -209,6 +210,31 @@ static const VMStateDescription vmstate_pmsav7_rnr =3D= { } }; =20 +static bool pmsav8_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V8); +} + +static const VMStateDescription vmstate_pmsav8 =3D { + .name =3D "cpu/pmsav8", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pmsav8_needed, + .fields =3D (VMStateField[]) { + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_UINT32(env.pmsav8.mair0, ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair1, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static int get_cpsr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503417561923103.43312944994284; Tue, 22 Aug 2017 08:59:21 -0700 (PDT) Received: from localhost ([::1]:57088 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBaK-0000l6-Pf for importer@patchew.org; Tue, 22 Aug 2017 11:59:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53562) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnw-0006dq-E0 for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAns-0003JB-Dx for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:20 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36966) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnm-00039F-HW; Tue, 22 Aug 2017 11:09:10 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAna-0004e0-Gg; Tue, 22 Aug 2017 16:08:58 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:41 +0100 Message-Id: <1503414539-28762-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 02/20] target/arm: Implement new PMSAv8 behaviour X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement the behavioural side of the new PMSAv8 specification. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 110 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7920153..887490a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8416,6 +8416,111 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, = uint32_t address, return !(*prot & (1 << access_type)); } =20 +static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_= idx, + hwaddr *phys_ptr, int *prot, uint32_t *fs= r) +{ + ARMCPU *cpu =3D arm_env_get_cpu(env); + bool is_user =3D regime_is_user(env, mmu_idx); + int n; + int matchregion =3D -1; + bool hit =3D false; + + *phys_ptr =3D address; + *prot =3D 0; + + /* Unlike the ARM ARM pseudocode, we don't need to check whether this + * was an exception vector read from the vector table (which is always + * done using the default system address map), because those accesses + * are done in arm_v7m_load_vector(), which always does a direct + * read using address_space_ldl(), rather than going via this function. + */ + if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ + hit =3D true; + } else if (m_is_ppb_region(env, address)) { + hit =3D true; + } else if (pmsav7_use_background_region(cpu, mmu_idx, is_user)) { + hit =3D true; + } else { + for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { + /* region search */ + /* Note that the base address is bits [31:5] from the register + * with bits [4:0] all zeroes, but the limit address is bits + * [31:5] from the register with bits [4:0] all ones. + */ + uint32_t base =3D env->pmsav8.rbar[n] & ~0x1f; + uint32_t limit =3D env->pmsav8.rlar[n] | 0x1f; + + if (!(env->pmsav8.rlar[n] & 0x1)) { + /* Region disabled */ + continue; + } + + if (address < base || address > limit) { + continue; + } + + if (hit) { + /* Multiple regions match -- always a failure (unlike + * PMSAv7 where highest-numbered-region wins) + */ + *fsr =3D 0x00d; /* permission fault */ + return true; + } + + matchregion =3D n; + hit =3D true; + + if (base & ~TARGET_PAGE_MASK) { + qemu_log_mask(LOG_UNIMP, + "MPU_RBAR[%d]: No support for MPU region bas= e" + "address of 0x%" PRIx32 ". Minimum alignment= is " + "%d\n", + n, base, TARGET_PAGE_BITS); + continue; + } + if ((limit + 1) & ~TARGET_PAGE_MASK) { + qemu_log_mask(LOG_UNIMP, + "MPU_RBAR[%d]: No support for MPU region lim= it" + "address of 0x%" PRIx32 ". Minimum alignment= is " + "%d\n", + n, limit, TARGET_PAGE_BITS); + continue; + } + } + } + + if (!hit) { + /* background fault */ + *fsr =3D 0; + return true; + } + + if (matchregion =3D=3D -1) { + /* hit using the background region */ + get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + } else { + uint32_t ap =3D extract32(env->pmsav8.rbar[matchregion], 1, 2); + uint32_t xn =3D extract32(env->pmsav8.rbar[matchregion], 0, 1); + + if (m_is_system_region(env, address)) { + /* System space is always execute never */ + xn =3D 1; + } + + *prot =3D simple_ap_to_rw_prot(env, mmu_idx, ap); + if (*prot && !xn) { + *prot |=3D PAGE_EXEC; + } + /* We don't need to look the attribute up in the MAIR0/MAIR1 + * registers because that only tells us about cacheability. + */ + } + + *fsr =3D 0x00d; /* Permission fault */ + return !(*prot & (1 << access_type)); +} + static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_= idx, hwaddr *phys_ptr, int *prot, uint32_t *fs= r) @@ -8585,7 +8690,11 @@ static bool get_phys_addr(CPUARMState *env, target_u= long address, bool ret; *page_size =3D TARGET_PAGE_SIZE; =20 - if (arm_feature(env, ARM_FEATURE_V7)) { + if (arm_feature(env, ARM_FEATURE_V8)) { + /* PMSAv8 */ + ret =3D get_phys_addr_pmsav8(env, address, access_type, mmu_id= x, + phys_ptr, prot, fsr); + } else if (arm_feature(env, ARM_FEATURE_V7)) { /* PMSAv7 */ ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_id= x, phys_ptr, prot, fsr); --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503416868104768.3215614883775; Tue, 22 Aug 2017 08:47:48 -0700 (PDT) Received: from localhost ([::1]:56001 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBP8-0007iv-Rs for importer@patchew.org; Tue, 22 Aug 2017 11:47:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53587) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnx-0006f9-5q for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnt-0003K6-Ic for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:21 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36936) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnl-00031e-LI; Tue, 22 Aug 2017 11:09:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnb-0004eF-6B; Tue, 22 Aug 2017 16:08:59 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:42 +0100 Message-Id: <1503414539-28762-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 03/20] target/arm: Add state field, feature bit and migration for v8M secure state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As the first step in implementing ARM v8M's security extension: * add a new feature bit ARM_FEATURE_M_SECURITY * add the CPU state field that indicates whether the CPU is currently in the secure state * add a migration subsection for this new state (we will add the Secure copies of banked register state to this subsection in later patches) * add a #define for the one new-in-v8M exception type * make the CPU debug log print S/NS status Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.h | 3 +++ target/arm/cpu.c | 4 ++++ target/arm/machine.c | 20 ++++++++++++++++++++ target/arm/translate.c | 8 +++++++- 4 files changed, 34 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b6bb78a..24666baa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -66,6 +66,7 @@ #define ARMV7M_EXCP_MEM 4 #define ARMV7M_EXCP_BUS 5 #define ARMV7M_EXCP_USAGE 6 +#define ARMV7M_EXCP_SECURE 7 #define ARMV7M_EXCP_SVC 11 #define ARMV7M_EXCP_DEBUG 12 #define ARMV7M_EXCP_PENDSV 14 @@ -420,6 +421,7 @@ typedef struct CPUARMState { int exception; uint32_t primask; uint32_t faultmask; + uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; =20 /* Information associated with an exception about to be taken: @@ -1264,6 +1266,7 @@ enum arm_features { ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */ ARM_FEATURE_PMU, /* has PMU support */ ARM_FEATURE_VBAR, /* has cp15 VBAR */ + ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8b610de..f32317e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -185,6 +185,10 @@ static void arm_cpu_reset(CPUState *s) uint32_t initial_pc; /* Loaded from 0x4 */ uint8_t *rom; =20 + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + env->v7m.secure =3D true; + } + /* The reset value of this bit is IMPDEF, but ARM recommends * that it resets to 1, so QEMU always does that rather than making * it dependent on CPU model. diff --git a/target/arm/machine.c b/target/arm/machine.c index 05e2909..745adae 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -235,6 +235,25 @@ static const VMStateDescription vmstate_pmsav8 =3D { } }; =20 +static bool m_security_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return arm_feature(env, ARM_FEATURE_M_SECURITY); +} + +static const VMStateDescription vmstate_m_security =3D { + .name =3D "cpu/m-security", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D m_security_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32(env.v7m.secure, ARMCPU), + VMSTATE_END_OF_LIST() + } +}; + static int get_cpsr(QEMUFile *f, void *opaque, size_t size, VMStateField *field) { @@ -484,6 +503,7 @@ const VMStateDescription vmstate_arm_cpu =3D { */ &vmstate_pmsav7_rnr, &vmstate_pmsav7, + &vmstate_m_security, NULL } }; diff --git a/target/arm/translate.c b/target/arm/translate.c index e52a6d7..dea0a6f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12232,6 +12232,11 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fpr= intf_function cpu_fprintf, if (arm_feature(env, ARM_FEATURE_M)) { uint32_t xpsr =3D xpsr_read(env); const char *mode; + const char *ns_status =3D ""; + + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + ns_status =3D env->v7m.secure ? "S " : "NS "; + } =20 if (xpsr & XPSR_EXCP) { mode =3D "handler"; @@ -12243,13 +12248,14 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fp= rintf_function cpu_fprintf, } } =20 - cpu_fprintf(f, "XPSR=3D%08x %c%c%c%c %c %s\n", + cpu_fprintf(f, "XPSR=3D%08x %c%c%c%c %c %s%s\n", xpsr, xpsr & XPSR_N ? 'N' : '-', xpsr & XPSR_Z ? 'Z' : '-', xpsr & XPSR_C ? 'C' : '-', xpsr & XPSR_V ? 'V' : '-', xpsr & XPSR_T ? 'T' : 'A', + ns_status, mode); } else { uint32_t psr =3D cpsr_read(env); --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503417363181569.5258546362163; Tue, 22 Aug 2017 08:56:03 -0700 (PDT) Received: from localhost ([::1]:56823 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBX7-0006Pn-PW for importer@patchew.org; Tue, 22 Aug 2017 11:56:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53488) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnt-0006Yh-8k for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAno-0003Ev-Or for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:17 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnl-00037y-IQ; Tue, 22 Aug 2017 11:09:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnc-0004eU-4e; Tue, 22 Aug 2017 16:09:00 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:43 +0100 Message-Id: <1503414539-28762-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 04/20] target/arm: Register second AddressSpace for secure v8M CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If a v8M CPU supports the security extension then we need to give it two AddressSpaces, the same way we do already for an A profile core with EL3. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f32317e..ae866be 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -843,22 +843,21 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) init_cpreg_list(cpu); =20 #ifndef CONFIG_USER_ONLY - if (cpu->has_el3) { - cs->num_ases =3D 2; - } else { - cs->num_ases =3D 1; - } - - if (cpu->has_el3) { + if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) { AddressSpace *as; =20 + cs->num_ases =3D 2; + if (!cpu->secure_memory) { cpu->secure_memory =3D cs->memory; } as =3D address_space_init_shareable(cpu->secure_memory, "cpu-secure-memory"); cpu_address_space_init(cs, as, ARMASIdx_S); + } else { + cs->num_ases =3D 1; } + cpu_address_space_init(cs, address_space_init_shareable(cs->memory, "cpu-memory"), --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503417274656828.9051198043524; Tue, 22 Aug 2017 08:54:34 -0700 (PDT) Received: from localhost ([::1]:56813 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBVh-00057W-C3 for importer@patchew.org; Tue, 22 Aug 2017 11:54:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53707) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAo1-0006lS-Sk for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAo0-0003PM-OL for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:25 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36966) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnl-00039F-5Y; Tue, 22 Aug 2017 11:09:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnc-0004fF-RV; Tue, 22 Aug 2017 16:09:00 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:44 +0100 Message-Id: <1503414539-28762-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 05/20] target/arm: Add MMU indexes for secure v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Now that MPU lookups can return different results for v8M when the CPU is in secure vs non-secure state, we need to have separate MMU indexes; add the secure counterparts to the existing three M profile MMU indexes. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 19 +++++++++++++++++-- target/arm/helper.c | 9 ++++++++- 2 files changed, 25 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 24666baa..436ca0d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2104,6 +2104,10 @@ static inline bool arm_excp_unmasked(CPUState *cs, u= nsigned int excp_idx, * Execution priority negative (this is like privileged, but the * MPU HFNMIENA bit means that it may have different access permission * check results to normal privileged code, so can't share a TLB). + * If the CPU supports the v8M Security Extension then there are also: + * Secure User + * Secure Privileged + * Secure, execution priority negative * * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code * are not quite the same -- different CPU types (most notably M profile @@ -2141,6 +2145,9 @@ typedef enum ARMMMUIdx { ARMMMUIdx_MUser =3D 0 | ARM_MMU_IDX_M, ARMMMUIdx_MPriv =3D 1 | ARM_MMU_IDX_M, ARMMMUIdx_MNegPri =3D 2 | ARM_MMU_IDX_M, + ARMMMUIdx_MSUser =3D 3 | ARM_MMU_IDX_M, + ARMMMUIdx_MSPriv =3D 4 | ARM_MMU_IDX_M, + ARMMMUIdx_MSNegPri =3D 5 | ARM_MMU_IDX_M, /* Indexes below here don't have TLBs and are used only for AT system * instructions or for the first stage of an S12 page table walk. */ @@ -2162,6 +2169,9 @@ typedef enum ARMMMUIdxBit { ARMMMUIdxBit_MUser =3D 1 << 0, ARMMMUIdxBit_MPriv =3D 1 << 1, ARMMMUIdxBit_MNegPri =3D 1 << 2, + ARMMMUIdxBit_MSUser =3D 1 << 3, + ARMMMUIdxBit_MSPriv =3D 1 << 4, + ARMMMUIdxBit_MSNegPri =3D 1 << 5, } ARMMMUIdxBit; =20 #define MMU_USER_IDX 0 @@ -2187,7 +2197,8 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) case ARM_MMU_IDX_A: return mmu_idx & 3; case ARM_MMU_IDX_M: - return mmu_idx =3D=3D ARMMMUIdx_MUser ? 0 : 1; + return (mmu_idx =3D=3D ARMMMUIdx_MUser || mmu_idx =3D=3D ARMMMUIdx= _MSUser) + ? 0 : 1; default: g_assert_not_reached(); } @@ -2206,7 +2217,11 @@ static inline int cpu_mmu_index(CPUARMState *env, bo= ol ifetch) */ if ((env->v7m.exception > 0 && env->v7m.exception <=3D 3) || env->v7m.faultmask) { - return arm_to_core_mmu_idx(ARMMMUIdx_MNegPri); + mmu_idx =3D ARMMMUIdx_MNegPri; + } + + if (env->v7m.secure) { + mmu_idx +=3D ARMMMUIdx_MSUser; } =20 return arm_to_core_mmu_idx(mmu_idx); diff --git a/target/arm/helper.c b/target/arm/helper.c index 887490a..1debebc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7037,6 +7037,9 @@ static inline uint32_t regime_el(CPUARMState *env, AR= MMMUIdx mmu_idx) case ARMMMUIdx_MPriv: case ARMMMUIdx_MNegPri: case ARMMMUIdx_MUser: + case ARMMMUIdx_MSPriv: + case ARMMMUIdx_MSNegPri: + case ARMMMUIdx_MSUser: return 1; default: g_assert_not_reached(); @@ -7060,6 +7063,9 @@ static inline bool regime_is_secure(CPUARMState *env,= ARMMMUIdx mmu_idx) case ARMMMUIdx_S1E3: case ARMMMUIdx_S1SE0: case ARMMMUIdx_S1SE1: + case ARMMMUIdx_MSPriv: + case ARMMMUIdx_MSNegPri: + case ARMMMUIdx_MSUser: return true; default: g_assert_not_reached(); @@ -7081,7 +7087,8 @@ static inline bool regime_translation_disabled(CPUARM= State *env, (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK= )) { case R_V7M_MPU_CTRL_ENABLE_MASK: /* Enabled, but not for HardFault and NMI */ - return mmu_idx =3D=3D ARMMMUIdx_MNegPri; + return mmu_idx =3D=3D ARMMMUIdx_MNegPri || + mmu_idx =3D=3D ARMMMUIdx_MSNegPri; case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK: /* Enabled for all cases */ return false; --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503416285069188.03809645922797; Tue, 22 Aug 2017 08:38:05 -0700 (PDT) Received: from localhost ([::1]:55172 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBFj-0005wp-9J for importer@patchew.org; Tue, 22 Aug 2017 11:38:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53367) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnp-0006TX-0J for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnn-0003De-IO for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:12 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36936) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnk-00031e-KS; Tue, 22 Aug 2017 11:09:08 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnd-0004fk-J2; Tue, 22 Aug 2017 16:09:01 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:45 +0100 Message-Id: <1503414539-28762-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 06/20] target/arm: Make BASEPRI register banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the BASEPRI register banked if v8M security extensions are enabled. Note that we do not yet implement the functionality of the new AIRCR.PRIS bit (which allows the effect of the NS copy of BASEPRI to be restricted). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.h | 14 +++++++++++++- hw/intc/armv7m_nvic.c | 4 ++-- target/arm/helper.c | 10 ++++++---- target/arm/machine.c | 3 ++- 4 files changed, 23 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 436ca0d..0c28dfd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -72,6 +72,18 @@ #define ARMV7M_EXCP_PENDSV 14 #define ARMV7M_EXCP_SYSTICK 15 =20 +/* For M profile, some registers are banked secure vs non-secure; + * these are represented as a 2-element array where the first element + * is the non-secure copy and the second is the secure copy. + * When the CPU does not have implement the security extension then + * only the first element is used. + * This means that the copy for the current security state can be + * accessed via env->registerfield[env->v7m.secure] (whether the security + * extension is implemented or not). + */ +#define M_REG_NS 0 +#define M_REG_S 1 + /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 @@ -409,7 +421,7 @@ typedef struct CPUARMState { struct { uint32_t other_sp; uint32_t vecbase; - uint32_t basepri; + uint32_t basepri[2]; uint32_t control; uint32_t ccr; /* Configuration and Control */ uint32_t cfsr; /* Configurable Fault Status */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index c0dbbad..2a41e5d 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -171,8 +171,8 @@ static inline int nvic_exec_prio(NVICState *s) running =3D -1; } else if (env->v7m.primask) { running =3D 0; - } else if (env->v7m.basepri > 0) { - running =3D env->v7m.basepri & nvic_gprio_mask(s); + } else if (env->v7m.basepri[env->v7m.secure] > 0) { + running =3D env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s); } else { running =3D NVIC_NOEXC_PRIO; /* lower than any possible priority */ } diff --git a/target/arm/helper.c b/target/arm/helper.c index 1debebc..1087f19 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8838,7 +8838,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t r= eg) return env->v7m.primask; case 17: /* BASEPRI */ case 18: /* BASEPRI_MAX */ - return env->v7m.basepri; + return env->v7m.basepri[env->v7m.secure]; case 19: /* FAULTMASK */ return env->v7m.faultmask; default: @@ -8898,12 +8898,14 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t mas= kreg, uint32_t val) env->v7m.primask =3D val & 1; break; case 17: /* BASEPRI */ - env->v7m.basepri =3D val & 0xff; + env->v7m.basepri[env->v7m.secure] =3D val & 0xff; break; case 18: /* BASEPRI_MAX */ val &=3D 0xff; - if (val !=3D 0 && (val < env->v7m.basepri || env->v7m.basepri =3D= =3D 0)) - env->v7m.basepri =3D val; + if (val !=3D 0 && (val < env->v7m.basepri[env->v7m.secure] + || env->v7m.basepri[env->v7m.secure] =3D=3D 0)) { + env->v7m.basepri[env->v7m.secure] =3D val; + } break; case 19: /* FAULTMASK */ env->v7m.faultmask =3D val & 1; diff --git a/target/arm/machine.c b/target/arm/machine.c index 745adae..8476efd 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -115,7 +115,7 @@ static const VMStateDescription vmstate_m =3D { .needed =3D m_needed, .fields =3D (VMStateField[]) { VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), - VMSTATE_UINT32(env.v7m.basepri, ARMCPU), + VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.control, ARMCPU), VMSTATE_UINT32(env.v7m.ccr, ARMCPU), VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), @@ -250,6 +250,7 @@ static const VMStateDescription vmstate_m_security =3D { .needed =3D m_security_needed, .fields =3D (VMStateField[]) { VMSTATE_UINT32(env.v7m.secure, ARMCPU), + VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503415970977531.865168487561; Tue, 22 Aug 2017 08:32:50 -0700 (PDT) Received: from localhost ([::1]:54594 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBAf-00014E-Lp for importer@patchew.org; Tue, 22 Aug 2017 11:32:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53349) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAno-0006QJ-Da for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnm-0003D1-VV for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:12 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36936) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnj-00031e-KT; Tue, 22 Aug 2017 11:09:07 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAne-0004fz-9a; Tue, 22 Aug 2017 16:09:02 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:46 +0100 Message-Id: <1503414539-28762-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 07/20] target/arm: Make PRIMASK register banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the PRIMASK register banked if v8M security extensions are enabled. Note that we do not yet implement the functionality of the new AIRCR.PRIS bit (which allows the effect of the NS copy of PRIMASK to be restricted). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 2 +- target/arm/helper.c | 4 ++-- target/arm/machine.c | 9 +++++++-- 4 files changed, 11 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0c28dfd..fee337b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -431,7 +431,7 @@ typedef struct CPUARMState { uint32_t bfar; /* BusFault Address */ unsigned mpu_ctrl; /* MPU_CTRL */ int exception; - uint32_t primask; + uint32_t primask[2]; uint32_t faultmask; uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2a41e5d..a654792 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -169,7 +169,7 @@ static inline int nvic_exec_prio(NVICState *s) =20 if (env->v7m.faultmask) { running =3D -1; - } else if (env->v7m.primask) { + } else if (env->v7m.primask[env->v7m.secure]) { running =3D 0; } else if (env->v7m.basepri[env->v7m.secure] > 0) { running =3D env->v7m.basepri[env->v7m.secure] & nvic_gprio_mask(s); diff --git a/target/arm/helper.c b/target/arm/helper.c index 1087f19..c0a6dbd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8835,7 +8835,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t r= eg) return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? env->regs[13] : env->v7m.other_sp; case 16: /* PRIMASK */ - return env->v7m.primask; + return env->v7m.primask[env->v7m.secure]; case 17: /* BASEPRI */ case 18: /* BASEPRI_MAX */ return env->v7m.basepri[env->v7m.secure]; @@ -8895,7 +8895,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) } break; case 16: /* PRIMASK */ - env->v7m.primask =3D val & 1; + env->v7m.primask[env->v7m.secure] =3D val & 1; break; case 17: /* BASEPRI */ env->v7m.basepri[env->v7m.secure] =3D val & 0xff; diff --git a/target/arm/machine.c b/target/arm/machine.c index 8476efd..6f0f6c9 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -103,7 +103,7 @@ static const VMStateDescription vmstate_m_faultmask_pri= mask =3D { .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), - VMSTATE_UINT32(env.v7m.primask, ARMCPU), + VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() } }; @@ -251,6 +251,7 @@ static const VMStateDescription vmstate_m_security =3D { .fields =3D (VMStateField[]) { VMSTATE_UINT32(env.v7m.secure, ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; @@ -271,9 +272,13 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t = size, * differences are that the T bit is not in the same place, the * primask/faultmask info may be in the CPSR I and F bits, and * we do not want the mode bits. + * We know that this cleanup happened before v8M, so there + * is no complication with banked primask/faultmask. */ uint32_t newval =3D val; =20 + assert(!arm_feature(env, ARM_FEATURE_M_SECURITY)); + newval &=3D (CPSR_NZCV | CPSR_Q | CPSR_IT | CPSR_GE); if (val & CPSR_T) { newval |=3D XPSR_T; @@ -287,7 +292,7 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t s= ize, env->v7m.faultmask =3D 1; } if (val & CPSR_I) { - env->v7m.primask =3D 1; + env->v7m.primask[M_REG_NS] =3D 1; } val =3D newval; } --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503417183268573.4019662970766; Tue, 22 Aug 2017 08:53:03 -0700 (PDT) Received: from localhost ([::1]:56557 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBUD-0003eU-H3 for importer@patchew.org; Tue, 22 Aug 2017 11:53:01 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53442) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnr-0006Vm-DI for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnm-0003Ca-Jb for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:15 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36936) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnh-00031e-Lj; Tue, 22 Aug 2017 11:09:05 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnf-0004gf-2e; Tue, 22 Aug 2017 16:09:03 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:47 +0100 Message-Id: <1503414539-28762-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 08/20] target/arm: Make FAULTMASK register banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the FAULTMASK register banked if v8M security extensions are enabled. Note that we do not yet implement the functionality of the new AIRCR.PRIS bit (which allows the effect of the NS copy of FAULTMASK to be restricted). This patch includes the code to determine for v8M which copy of FAULTMASK should be updated on exception exit; further changes will be required to the exception exit code in general to support v8M, so this is just a small piece of that. The v8M ARM ARM introduces a notation where individual paragraphs are labelled with R (for rule) or I (for information) followed by a random group of subscript letters. In comments where we want to refer to a particular part of the manual we use this convention, which should be more stable across document revisions than using section or page numbers. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 14 ++++++++++++-- hw/intc/armv7m_nvic.c | 9 ++++++++- target/arm/helper.c | 20 ++++++++++++++++---- target/arm/machine.c | 5 +++-- 4 files changed, 39 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fee337b..edd4c9e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -432,7 +432,7 @@ typedef struct CPUARMState { unsigned mpu_ctrl; /* MPU_CTRL */ int exception; uint32_t primask[2]; - uint32_t faultmask; + uint32_t faultmask[2]; uint32_t secure; /* Is CPU in Secure state? (not guest visible) */ } v7m; =20 @@ -1443,6 +1443,16 @@ void armv7m_nvic_acknowledge_irq(void *opaque); * (Ignoring -1, this is the same as the RETTOBASE value before completion= .) */ int armv7m_nvic_complete_irq(void *opaque, int irq); +/** + * armv7m_nvic_raw_execution_priority: return the raw execution priority + * @opaque: the NVIC + * + * Returns: the raw execution priority as defined by the v8M architecture. + * This is the execution priority minus the effects of AIRCR.PRIS, + * and minus any PRIMASK/FAULTMASK/BASEPRI priority boosting. + * (v8M ARM ARM I_PKLD.) + */ +int armv7m_nvic_raw_execution_priority(void *opaque); =20 /* Interface for defining coprocessor registers. * Registers are defined in tables of arm_cp_reginfo structs @@ -2228,7 +2238,7 @@ static inline int cpu_mmu_index(CPUARMState *env, boo= l ifetch) * we're in a HardFault or NMI handler. */ if ((env->v7m.exception > 0 && env->v7m.exception <=3D 3) - || env->v7m.faultmask) { + || env->v7m.faultmask[env->v7m.secure]) { mmu_idx =3D ARMMMUIdx_MNegPri; } =20 diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index a654792..babdc3b 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -167,7 +167,7 @@ static inline int nvic_exec_prio(NVICState *s) CPUARMState *env =3D &s->cpu->env; int running; =20 - if (env->v7m.faultmask) { + if (env->v7m.faultmask[env->v7m.secure]) { running =3D -1; } else if (env->v7m.primask[env->v7m.secure]) { running =3D 0; @@ -187,6 +187,13 @@ bool armv7m_nvic_can_take_pending_exception(void *opaq= ue) return nvic_exec_prio(s) > nvic_pending_prio(s); } =20 +int armv7m_nvic_raw_execution_priority(void *opaque) +{ + NVICState *s =3D opaque; + + return s->exception_prio; +} + /* caller must call nvic_irq_update() after this */ static void set_prio(NVICState *s, unsigned irq, uint8_t prio) { diff --git a/target/arm/helper.c b/target/arm/helper.c index c0a6dbd..b8f3b23 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6171,8 +6171,20 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } =20 if (env->v7m.exception !=3D ARMV7M_EXCP_NMI) { - /* Auto-clear FAULTMASK on return from other than NMI */ - env->v7m.faultmask =3D 0; + /* Auto-clear FAULTMASK on return from other than NMI. + * If the security extension is implemented then this only + * happens if the raw execution priority is >=3D 0; the + * value of the ES bit in the exception return value indicates + * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) + */ + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + int es =3D type & 1; + if (armv7m_nvic_raw_execution_priority(env->nvic) >=3D 0) { + env->v7m.faultmask[es] =3D 0; + } + } else { + env->v7m.faultmask[M_REG_NS] =3D 0; + } } =20 switch (armv7m_nvic_complete_irq(env->nvic, env->v7m.exception)) { @@ -8840,7 +8852,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t r= eg) case 18: /* BASEPRI_MAX */ return env->v7m.basepri[env->v7m.secure]; case 19: /* FAULTMASK */ - return env->v7m.faultmask; + return env->v7m.faultmask[env->v7m.secure]; default: qemu_log_mask(LOG_GUEST_ERROR, "Attempt to read unknown special" " register %d\n", reg); @@ -8908,7 +8920,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) } break; case 19: /* FAULTMASK */ - env->v7m.faultmask =3D val & 1; + env->v7m.faultmask[env->v7m.secure] =3D val & 1; break; case 20: /* CONTROL */ /* Writing to the SPSEL bit only has an effect if we are in diff --git a/target/arm/machine.c b/target/arm/machine.c index 6f0f6c9..bd7aba1 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -102,7 +102,7 @@ static const VMStateDescription vmstate_m_faultmask_pri= mask =3D { .version_id =3D 1, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { - VMSTATE_UINT32(env.v7m.faultmask, ARMCPU), + VMSTATE_UINT32(env.v7m.faultmask[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.primask[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() } @@ -252,6 +252,7 @@ static const VMStateDescription vmstate_m_security =3D { VMSTATE_UINT32(env.v7m.secure, ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; @@ -289,7 +290,7 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t s= ize, * transferred using the vmstate_m_faultmask_primask subsectio= n. */ if (val & CPSR_F) { - env->v7m.faultmask =3D 1; + env->v7m.faultmask[M_REG_NS] =3D 1; } if (val & CPSR_I) { env->v7m.primask[M_REG_NS] =3D 1; --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503416285140844.432376553012; Tue, 22 Aug 2017 08:38:05 -0700 (PDT) Received: from localhost ([::1]:55178 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBFj-0005y5-4I for importer@patchew.org; Tue, 22 Aug 2017 11:38:03 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53630) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAny-0006go-98 for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnu-0003Ka-C4 for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:22 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnj-00037y-HK; Tue, 22 Aug 2017 11:09:07 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnf-0004h9-Q5; Tue, 22 Aug 2017 16:09:03 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:48 +0100 Message-Id: <1503414539-28762-10-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 09/20] target/arm: Make CONTROL register banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the CONTROL register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 +++-- target/arm/helper.c | 21 +++++++++++---------- target/arm/machine.c | 3 ++- target/arm/translate.c | 2 +- 4 files changed, 17 insertions(+), 14 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index edd4c9e..e922d1f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -422,7 +422,7 @@ typedef struct CPUARMState { uint32_t other_sp; uint32_t vecbase; uint32_t basepri[2]; - uint32_t control; + uint32_t control[2]; uint32_t ccr; /* Configuration and Control */ uint32_t cfsr; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ @@ -1682,7 +1682,8 @@ static inline bool arm_v7m_is_handler_mode(CPUARMStat= e *env) static inline int arm_current_el(CPUARMState *env) { if (arm_feature(env, ARM_FEATURE_M)) { - return arm_v7m_is_handler_mode(env) || !(env->v7m.control & 1); + return arm_v7m_is_handler_mode(env) || + !(env->v7m.control[env->v7m.secure] & 1); } =20 if (is_a64(env)) { diff --git a/target/arm/helper.c b/target/arm/helper.c index b8f3b23..8e74b10 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6053,14 +6053,15 @@ static uint32_t v7m_pop(CPUARMState *env) static void switch_v7m_sp(CPUARMState *env, bool new_spsel) { uint32_t tmp; - bool old_spsel =3D env->v7m.control & R_V7M_CONTROL_SPSEL_MASK; + uint32_t old_control =3D env->v7m.control[env->v7m.secure]; + bool old_spsel =3D old_control & R_V7M_CONTROL_SPSEL_MASK; =20 if (old_spsel !=3D new_spsel) { tmp =3D env->v7m.other_sp; env->v7m.other_sp =3D env->regs[13]; env->regs[13] =3D tmp; =20 - env->v7m.control =3D deposit32(env->v7m.control, + env->v7m.control[env->v7m.secure] =3D deposit32(old_control, R_V7M_CONTROL_SPSEL_SHIFT, R_V7M_CONTROL_SPSEL_LENGTH, new_spsel= ); } @@ -6414,7 +6415,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) } =20 lr =3D 0xfffffff1; - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { lr |=3D 4; } if (!arm_v7m_is_handler_mode(env)) { @@ -8832,7 +8833,7 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t r= eg) return xpsr_read(env) & mask; break; case 20: /* CONTROL */ - return env->v7m.control; + return env->v7m.control[env->v7m.secure]; } =20 if (el =3D=3D 0) { @@ -8841,10 +8842,10 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t= reg) =20 switch (reg) { case 8: /* MSP */ - return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? + return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MA= SK) ? env->v7m.other_sp : env->regs[13]; case 9: /* PSP */ - return (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) ? + return (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MA= SK) ? env->regs[13] : env->v7m.other_sp; case 16: /* PRIMASK */ return env->v7m.primask[env->v7m.secure]; @@ -8893,14 +8894,14 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t mas= kreg, uint32_t val) } break; case 8: /* MSP */ - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { env->v7m.other_sp =3D val; } else { env->regs[13] =3D val; } break; case 9: /* PSP */ - if (env->v7m.control & R_V7M_CONTROL_SPSEL_MASK) { + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK) { env->regs[13] =3D val; } else { env->v7m.other_sp =3D val; @@ -8931,8 +8932,8 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) if (!arm_v7m_is_handler_mode(env)) { switch_v7m_sp(env, (val & R_V7M_CONTROL_SPSEL_MASK) !=3D 0); } - env->v7m.control &=3D ~R_V7M_CONTROL_NPRIV_MASK; - env->v7m.control |=3D val & R_V7M_CONTROL_NPRIV_MASK; + env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_MASK; + env->v7m.control[env->v7m.secure] |=3D val & R_V7M_CONTROL_NPRIV_M= ASK; break; default: qemu_log_mask(LOG_GUEST_ERROR, "Attempt to write unknown special" diff --git a/target/arm/machine.c b/target/arm/machine.c index bd7aba1..2cd64c5 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -116,7 +116,7 @@ static const VMStateDescription vmstate_m =3D { .fields =3D (VMStateField[]) { VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), - VMSTATE_UINT32(env.v7m.control, ARMCPU), + VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.ccr, ARMCPU), VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), @@ -253,6 +253,7 @@ static const VMStateDescription vmstate_m_security =3D { VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; diff --git a/target/arm/translate.c b/target/arm/translate.c index dea0a6f..6aa2d7c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12241,7 +12241,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fpri= ntf_function cpu_fprintf, if (xpsr & XPSR_EXCP) { mode =3D "handler"; } else { - if (env->v7m.control & R_V7M_CONTROL_NPRIV_MASK) { + if (env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_NPRIV_MA= SK) { mode =3D "unpriv-thread"; } else { mode =3D "priv-thread"; --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503415337990538.0556743083375; Tue, 22 Aug 2017 08:22:17 -0700 (PDT) Received: from localhost ([::1]:53532 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkB0S-0000e0-3k for importer@patchew.org; Tue, 22 Aug 2017 11:22:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53482) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAns-0006XU-U5 for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnp-0003FQ-77 for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:16 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36936) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAni-00031e-Lm; Tue, 22 Aug 2017 11:09:06 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAng-0004ho-IY; Tue, 22 Aug 2017 16:09:04 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:49 +0100 Message-Id: <1503414539-28762-11-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 10/20] nvic: Add NS alias SCS region X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For v8M the range 0xe002e000..0xe002efff is an alias region which for secure accesses behaves like a NonSecure access to the main SCS region. (For nonsecure accesses including when the security extension is not implemented, it is RAZ/WI.) Signed-off-by: Peter Maydell --- include/hw/intc/armv7m_nvic.h | 1 + hw/intc/armv7m_nvic.c | 66 +++++++++++++++++++++++++++++++++++++++= +++- 2 files changed, 66 insertions(+), 1 deletion(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 1d145fb..1a4cce7 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -50,6 +50,7 @@ typedef struct NVICState { int exception_prio; /* group prio of the highest prio active exception= */ =20 MemoryRegion sysregmem; + MemoryRegion sysreg_ns_mem; MemoryRegion container; =20 uint32_t num_irq; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index babdc3b..2b0b328 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1040,6 +1040,47 @@ static const MemoryRegionOps nvic_sysreg_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +static MemTxResult nvic_sysreg_ns_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + if (attrs.secure) { + /* S accesses to the alias act like NS accesses to the real region= */ + attrs.secure =3D 0; + return nvic_sysreg_write(opaque, addr, value, size, attrs); + } else { + /* NS attrs are RAZ/WI for privileged, and BusFault for user */ + if (attrs.user) { + return MEMTX_ERROR; + } + return MEMTX_OK; + } +} + +static MemTxResult nvic_sysreg_ns_read(void *opaque, hwaddr addr, + uint64_t *data, unsigned size, + MemTxAttrs attrs) +{ + if (attrs.secure) { + /* S accesses to the alias act like NS accesses to the real region= */ + attrs.secure =3D 0; + return nvic_sysreg_read(opaque, addr, data, size, attrs); + } else { + /* NS attrs are RAZ/WI for privileged, and BusFault for user */ + if (attrs.user) { + return MEMTX_ERROR; + } + *data =3D 0; + return MEMTX_OK; + } +} + +static const MemoryRegionOps nvic_sysreg_ns_ops =3D { + .read_with_attrs =3D nvic_sysreg_ns_read, + .write_with_attrs =3D nvic_sysreg_ns_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, +}; + static int nvic_post_load(void *opaque, int version_id) { NVICState *s =3D opaque; @@ -1141,6 +1182,7 @@ static void armv7m_nvic_realize(DeviceState *dev, Err= or **errp) NVICState *s =3D NVIC(dev); SysBusDevice *systick_sbd; Error *err =3D NULL; + int regionlen; =20 s->cpu =3D ARM_CPU(qemu_get_cpu(0)); assert(s->cpu); @@ -1173,8 +1215,23 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) * 0xd00..0xd3c - SCS registers * 0xd40..0xeff - Reserved or Not implemented * 0xf00 - STIR + * + * Some registers within this space are banked between security states. + * In v8M there is a second range 0xe002e000..0xe002efff which is the + * NonSecure alias SCS; secure accesses to this behave like NS accesses + * to the main SCS range, and non-secure accesses (including when + * the security extension is not implemented) are RAZ/WI. + * Note that both the main SCS range and the alias range are defined + * to be exempt from memory attribution (R_BLJT) and so the memory + * transaction attribute always matches the current CPU security + * state (attrs.secure =3D=3D env->v7m.secure). In the nvic_sysreg_ns_= ops + * wrappers we change attrs.secure to indicate the NS access; so + * generally code determining which banked register to use should + * use attrs.secure; code determining actual behaviour of the system + * should use env->v7m.secure. */ - memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000); + regionlen =3D arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x= 1000; + memory_region_init(&s->container, OBJECT(s), "nvic", regionlen); /* The system register region goes at the bottom of the priority * stack as it covers the whole page. */ @@ -1185,6 +1242,13 @@ static void armv7m_nvic_realize(DeviceState *dev, Er= ror **errp) sysbus_mmio_get_region(systick_sbd= , 0), 1); =20 + if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) { + memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s), + &nvic_sysreg_ns_ops, s, + "nvic_sysregs_ns", 0x1000); + memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_= mem); + } + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container); } =20 --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503415547134812.64476335497; Tue, 22 Aug 2017 08:25:47 -0700 (PDT) Received: from localhost ([::1]:54011 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkB3p-0003dK-I7 for importer@patchew.org; Tue, 22 Aug 2017 11:25:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53543) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnv-0006cy-Pi for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAns-0003J4-CI for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:19 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAni-00037y-Gd; Tue, 22 Aug 2017 11:09:06 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnh-0004i6-H2; Tue, 22 Aug 2017 16:09:05 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:50 +0100 Message-Id: <1503414539-28762-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 11/20] target/arm: Make VTOR register banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the VTOR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 13 +++++++------ target/arm/helper.c | 2 +- target/arm/machine.c | 3 ++- 4 files changed, 11 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e922d1f..d0b0936 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -420,7 +420,7 @@ typedef struct CPUARMState { =20 struct { uint32_t other_sp; - uint32_t vecbase; + uint32_t vecbase[2]; uint32_t basepri[2]; uint32_t control[2]; uint32_t ccr; /* Configuration and Control */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 2b0b328..3a1f02d 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -403,7 +403,7 @@ static void set_irq_level(void *opaque, int n, int leve= l) } } =20 -static uint32_t nvic_readl(NVICState *s, uint32_t offset) +static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) { ARMCPU *cpu =3D s->cpu; uint32_t val; @@ -441,7 +441,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t) /* ISRPREEMPT not implemented */ return val; case 0xd08: /* Vector Table Offset. */ - return cpu->env.v7m.vecbase; + return cpu->env.v7m.vecbase[attrs.secure]; case 0xd0c: /* Application Interrupt/Reset Control. */ return 0xfa050000 | (s->prigroup << 8); case 0xd10: /* System Control. */ @@ -617,7 +617,8 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t) } } =20 -static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value) +static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, + MemTxAttrs attrs) { ARMCPU *cpu =3D s->cpu; =20 @@ -638,7 +639,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value) } break; case 0xd08: /* Vector Table Offset. */ - cpu->env.v7m.vecbase =3D value & 0xffffff80; + cpu->env.v7m.vecbase[attrs.secure] =3D value & 0xffffff80; break; case 0xd0c: /* Application Interrupt/Reset Control. */ if ((value >> 16) =3D=3D 0x05fa) { @@ -944,7 +945,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwadd= r addr, break; default: if (size =3D=3D 4) { - val =3D nvic_readl(s, offset); + val =3D nvic_readl(s, offset, attrs); } else { qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read of size %d at offset 0x%x\n", @@ -1025,7 +1026,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hw= addr addr, return MEMTX_OK; } if (size =3D=3D 4) { - nvic_writel(s, offset, value); + nvic_writel(s, offset, value, attrs); return MEMTX_OK; } qemu_log_mask(LOG_GUEST_ERROR, diff --git a/target/arm/helper.c b/target/arm/helper.c index 8e74b10..b1bb507 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6072,7 +6072,7 @@ static uint32_t arm_v7m_load_vector(ARMCPU *cpu) CPUState *cs =3D CPU(cpu); CPUARMState *env =3D &cpu->env; MemTxResult result; - hwaddr vec =3D env->v7m.vecbase + env->v7m.exception * 4; + hwaddr vec =3D env->v7m.vecbase[env->v7m.secure] + env->v7m.exception = * 4; uint32_t addr; =20 addr =3D address_space_ldl(cs->as, vec, diff --git a/target/arm/machine.c b/target/arm/machine.c index 2cd64c5..cd6b6af 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -114,7 +114,7 @@ static const VMStateDescription vmstate_m =3D { .minimum_version_id =3D 4, .needed =3D m_needed, .fields =3D (VMStateField[]) { - VMSTATE_UINT32(env.v7m.vecbase, ARMCPU), + VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.ccr, ARMCPU), @@ -254,6 +254,7 @@ static const VMStateDescription vmstate_m_security =3D { VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503415112091859.7000735376031; Tue, 22 Aug 2017 08:18:32 -0700 (PDT) Received: from localhost ([::1]:53186 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAwo-00065K-Rs for importer@patchew.org; Tue, 22 Aug 2017 11:18:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53399) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnp-0006Va-Qn for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAno-0003EK-A2 for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:13 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnk-00037y-Hz; Tue, 22 Aug 2017 11:09:08 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAni-0004in-99; Tue, 22 Aug 2017 16:09:06 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:51 +0100 Message-Id: <1503414539-28762-13-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 12/20] target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- hw/intc/armv7m_nvic.c | 8 ++++---- target/arm/cpu.c | 4 ++-- target/arm/machine.c | 6 ++++-- 4 files changed, 12 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d0b0936..2f59828 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -545,8 +545,8 @@ typedef struct CPUARMState { */ uint32_t *rbar; uint32_t *rlar; - uint32_t mair0; - uint32_t mair1; + uint32_t mair0[2]; + uint32_t mair1[2]; } pmsav8; =20 void *nvic; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 3a1f02d..e98eb95 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -604,12 +604,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { goto bad_offset; } - return cpu->env.pmsav8.mair0; + return cpu->env.pmsav8.mair0[attrs.secure]; case 0xdc4: /* MPU_MAIR1 */ if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { goto bad_offset; } - return cpu->env.pmsav8.mair1; + return cpu->env.pmsav8.mair1[attrs.secure]; default: bad_offset: qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", off= set); @@ -826,7 +826,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value, } if (cpu->pmsav7_dregion) { /* Register is RES0 if no MPU regions are implemented */ - cpu->env.pmsav8.mair0 =3D value; + cpu->env.pmsav8.mair0[attrs.secure] =3D value; } /* We don't need to do anything else because memory attributes * only affect cacheability, and we don't implement caching. @@ -838,7 +838,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value, } if (cpu->pmsav7_dregion) { /* Register is RES0 if no MPU regions are implemented */ - cpu->env.pmsav8.mair1 =3D value; + cpu->env.pmsav8.mair1[attrs.secure] =3D value; } /* We don't need to do anything else because memory attributes * only affect cacheability, and we don't implement caching. diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ae866be..ae8af19 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -249,8 +249,8 @@ static void arm_cpu_reset(CPUState *s) } } env->pmsav7.rnr =3D 0; - env->pmsav8.mair0 =3D 0; - env->pmsav8.mair1 =3D 0; + memset(env->pmsav8.mair0, 0, sizeof(env->pmsav8.mair0)); + memset(env->pmsav8.mair1, 0, sizeof(env->pmsav8.mair1)); } =20 set_flush_to_zero(1, &env->vfp.standard_fp_status); diff --git a/target/arm/machine.c b/target/arm/machine.c index cd6b6af..414a879 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -229,8 +229,8 @@ static const VMStateDescription vmstate_pmsav8 =3D { vmstate_info_uint32, uint32_t), VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, vmstate_info_uint32, uint32_t), - VMSTATE_UINT32(env.pmsav8.mair0, ARMCPU), - VMSTATE_UINT32(env.pmsav8.mair1, ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() } }; @@ -255,6 +255,8 @@ static const VMStateDescription vmstate_m_security =3D { VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503416980379578.1398963551464; Tue, 22 Aug 2017 08:49:40 -0700 (PDT) Received: from localhost ([::1]:56341 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBQw-0000mv-U6 for importer@patchew.org; Tue, 22 Aug 2017 11:49:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53439) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnr-0006Vl-3a for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAno-0003ES-Ac for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:15 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36966) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnk-00039F-2M; Tue, 22 Aug 2017 11:09:08 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnj-0004j5-52; Tue, 22 Aug 2017 16:09:07 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:52 +0100 Message-Id: <1503414539-28762-14-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 13/20] target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the MPU registers MPU_MAIR0 and MPU_MAIR1 banked if v8M security extensions are enabled. We can freely add more items to vmstate_m_security without breaking migration compatibility, because no CPU currently has the ARM_FEATURE_M_SECURITY bit enabled and so this subsection is not yet used by anything. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- hw/intc/armv7m_nvic.c | 8 ++++---- target/arm/cpu.c | 26 ++++++++++++++++++++------ target/arm/helper.c | 11 ++++++----- target/arm/machine.c | 12 ++++++++---- 5 files changed, 40 insertions(+), 21 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 2f59828..12fa95e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -543,8 +543,8 @@ typedef struct CPUARMState { * pmsav7.rnr (region number register) * pmsav7_dregion (number of configured regions) */ - uint32_t *rbar; - uint32_t *rlar; + uint32_t *rbar[2]; + uint32_t *rlar[2]; uint32_t mair0[2]; uint32_t mair1[2]; } pmsav8; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index e98eb95..9ced7af 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -564,7 +564,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t, MemTxAttrs attrs) if (region >=3D cpu->pmsav7_dregion) { return 0; } - return cpu->env.pmsav8.rbar[region]; + return cpu->env.pmsav8.rbar[attrs.secure][region]; } =20 if (region >=3D cpu->pmsav7_dregion) { @@ -591,7 +591,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t, MemTxAttrs attrs) if (region >=3D cpu->pmsav7_dregion) { return 0; } - return cpu->env.pmsav8.rlar[region]; + return cpu->env.pmsav8.rlar[attrs.secure][region]; } =20 if (region >=3D cpu->pmsav7_dregion) { @@ -756,7 +756,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value, if (region >=3D cpu->pmsav7_dregion) { return; } - cpu->env.pmsav8.rbar[region] =3D value; + cpu->env.pmsav8.rbar[attrs.secure][region] =3D value; tlb_flush(CPU(cpu)); return; } @@ -806,7 +806,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value, if (region >=3D cpu->pmsav7_dregion) { return; } - cpu->env.pmsav8.rlar[region] =3D value; + cpu->env.pmsav8.rlar[attrs.secure][region] =3D value; tlb_flush(CPU(cpu)); return; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index ae8af19..333029c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -235,10 +235,20 @@ static void arm_cpu_reset(CPUState *s) if (arm_feature(env, ARM_FEATURE_PMSA)) { if (cpu->pmsav7_dregion > 0) { if (arm_feature(env, ARM_FEATURE_V8)) { - memset(env->pmsav8.rbar, 0, - sizeof(*env->pmsav8.rbar) * cpu->pmsav7_dregion); - memset(env->pmsav8.rlar, 0, - sizeof(*env->pmsav8.rlar) * cpu->pmsav7_dregion); + memset(env->pmsav8.rbar[M_REG_NS], 0, + sizeof(*env->pmsav8.rbar[M_REG_NS]) + * cpu->pmsav7_dregion); + memset(env->pmsav8.rlar[M_REG_NS], 0, + sizeof(*env->pmsav8.rlar[M_REG_NS]) + * cpu->pmsav7_dregion); + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + memset(env->pmsav8.rbar[M_REG_S], 0, + sizeof(*env->pmsav8.rbar[M_REG_S]) + * cpu->pmsav7_dregion); + memset(env->pmsav8.rlar[M_REG_S], 0, + sizeof(*env->pmsav8.rlar[M_REG_S]) + * cpu->pmsav7_dregion); + } } else if (arm_feature(env, ARM_FEATURE_V7)) { memset(env->pmsav7.drbar, 0, sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); @@ -823,8 +833,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Error = **errp) if (nr) { if (arm_feature(env, ARM_FEATURE_V8)) { /* PMSAv8 */ - env->pmsav8.rbar =3D g_new0(uint32_t, nr); - env->pmsav8.rlar =3D g_new0(uint32_t, nr); + env->pmsav8.rbar[M_REG_NS] =3D g_new0(uint32_t, nr); + env->pmsav8.rlar[M_REG_NS] =3D g_new0(uint32_t, nr); + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { + env->pmsav8.rbar[M_REG_S] =3D g_new0(uint32_t, nr); + env->pmsav8.rlar[M_REG_S] =3D g_new0(uint32_t, nr); + } } else { env->pmsav7.drbar =3D g_new0(uint32_t, nr); env->pmsav7.drsr =3D g_new0(uint32_t, nr); diff --git a/target/arm/helper.c b/target/arm/helper.c index b1bb507..5394cef 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8442,6 +8442,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, { ARMCPU *cpu =3D arm_env_get_cpu(env); bool is_user =3D regime_is_user(env, mmu_idx); + uint32_t secure =3D regime_is_secure(env, mmu_idx); int n; int matchregion =3D -1; bool hit =3D false; @@ -8468,10 +8469,10 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, = uint32_t address, * with bits [4:0] all zeroes, but the limit address is bits * [31:5] from the register with bits [4:0] all ones. */ - uint32_t base =3D env->pmsav8.rbar[n] & ~0x1f; - uint32_t limit =3D env->pmsav8.rlar[n] | 0x1f; + uint32_t base =3D env->pmsav8.rbar[secure][n] & ~0x1f; + uint32_t limit =3D env->pmsav8.rlar[secure][n] | 0x1f; =20 - if (!(env->pmsav8.rlar[n] & 0x1)) { + if (!(env->pmsav8.rlar[secure][n] & 0x1)) { /* Region disabled */ continue; } @@ -8520,8 +8521,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, ui= nt32_t address, /* hit using the background region */ get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); } else { - uint32_t ap =3D extract32(env->pmsav8.rbar[matchregion], 1, 2); - uint32_t xn =3D extract32(env->pmsav8.rbar[matchregion], 0, 1); + uint32_t ap =3D extract32(env->pmsav8.rbar[secure][matchregion], 1= , 2); + uint32_t xn =3D extract32(env->pmsav8.rbar[secure][matchregion], 0= , 1); =20 if (m_is_system_region(env, address)) { /* System space is always execute never */ diff --git a/target/arm/machine.c b/target/arm/machine.c index 414a879..05c6c7a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -225,10 +225,10 @@ static const VMStateDescription vmstate_pmsav8 =3D { .minimum_version_id =3D 1, .needed =3D pmsav8_needed, .fields =3D (VMStateField[]) { - VMSTATE_VARRAY_UINT32(env.pmsav8.rbar, ARMCPU, pmsav7_dregion, 0, - vmstate_info_uint32, uint32_t), - VMSTATE_VARRAY_UINT32(env.pmsav8.rlar, ARMCPU, pmsav7_dregion, 0, - vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_NS], ARMCPU, pmsav7_dr= egion, + 0, vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_NS], ARMCPU, pmsav7_dr= egion, + 0, vmstate_info_uint32, uint32_t), VMSTATE_UINT32(env.pmsav8.mair0[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair1[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() @@ -257,6 +257,10 @@ static const VMStateDescription vmstate_m_security =3D= { VMSTATE_UINT32(env.v7m.vecbase[M_REG_S], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair0[M_REG_S], ARMCPU), VMSTATE_UINT32(env.pmsav8.mair1[M_REG_S], ARMCPU), + VMSTATE_VARRAY_UINT32(env.pmsav8.rbar[M_REG_S], ARMCPU, pmsav7_dre= gion, + 0, vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dre= gion, + 0, vmstate_info_uint32, uint32_t), VMSTATE_END_OF_LIST() } }; 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Tue, 22 Aug 2017 11:09:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnz-0003OL-BH for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:28 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36984) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnr-0003E6-Ux; Tue, 22 Aug 2017 11:09:16 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnj-0004jb-UZ; Tue, 22 Aug 2017 16:09:07 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:53 +0100 Message-Id: <1503414539-28762-15-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 14/20] target/arm: Make MPU_RNR register banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the MPU_RNR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 18 +++++++++--------- target/arm/cpu.c | 3 ++- target/arm/helper.c | 6 +++--- target/arm/machine.c | 13 +++++++++++-- 5 files changed, 26 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 12fa95e..43d36d6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -533,7 +533,7 @@ typedef struct CPUARMState { uint32_t *drbar; uint32_t *drsr; uint32_t *dracr; - uint32_t rnr; + uint32_t rnr[2]; } pmsav7; =20 /* PMSAv8 MPU */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 9ced7af..c3c214c 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -543,13 +543,13 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) case 0xd94: /* MPU_CTRL */ return cpu->env.v7m.mpu_ctrl; case 0xd98: /* MPU_RNR */ - return cpu->env.pmsav7.rnr; + return cpu->env.pmsav7.rnr[attrs.secure]; case 0xd9c: /* MPU_RBAR */ case 0xda4: /* MPU_RBAR_A1 */ case 0xdac: /* MPU_RBAR_A2 */ case 0xdb4: /* MPU_RBAR_A3 */ { - int region =3D cpu->env.pmsav7.rnr; + int region =3D cpu->env.pmsav7.rnr[attrs.secure]; =20 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { /* PMSAv8M handling of the aliases is different from v7M: @@ -577,7 +577,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t, MemTxAttrs attrs) case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ { - int region =3D cpu->env.pmsav7.rnr; + int region =3D cpu->env.pmsav7.rnr[attrs.secure]; =20 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { /* PMSAv8M handling of the aliases is different from v7M: @@ -731,7 +731,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value, PRIu32 "/%" PRIu32 "\n", value, cpu->pmsav7_dregion); } else { - cpu->env.pmsav7.rnr =3D value; + cpu->env.pmsav7.rnr[attrs.secure] =3D value; } break; case 0xd9c: /* MPU_RBAR */ @@ -749,7 +749,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value, */ int aliasno =3D (offset - 0xd9c) / 8; /* 0..3 */ =20 - region =3D cpu->env.pmsav7.rnr; + region =3D cpu->env.pmsav7.rnr[attrs.secure]; if (aliasno) { region =3D deposit32(region, 0, 2, aliasno); } @@ -772,9 +772,9 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value, region, cpu->pmsav7_dregion); return; } - cpu->env.pmsav7.rnr =3D region; + cpu->env.pmsav7.rnr[attrs.secure] =3D region; } else { - region =3D cpu->env.pmsav7.rnr; + region =3D cpu->env.pmsav7.rnr[attrs.secure]; } =20 if (region >=3D cpu->pmsav7_dregion) { @@ -790,7 +790,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value, case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */ case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */ { - int region =3D cpu->env.pmsav7.rnr; + int region =3D cpu->env.pmsav7.rnr[attrs.secure]; =20 if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { /* PMSAv8M handling of the aliases is different from v7M: @@ -799,7 +799,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value, */ int aliasno =3D (offset - 0xd9c) / 8; /* 0..3 */ =20 - region =3D cpu->env.pmsav7.rnr; + region =3D cpu->env.pmsav7.rnr[attrs.secure]; if (aliasno) { region =3D deposit32(region, 0, 2, aliasno); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 333029c..11038b8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -258,7 +258,8 @@ static void arm_cpu_reset(CPUState *s) sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); } } - env->pmsav7.rnr =3D 0; + env->pmsav7.rnr[M_REG_NS] =3D 0; + env->pmsav7.rnr[M_REG_S] =3D 0; memset(env->pmsav8.mair0, 0, sizeof(env->pmsav8.mair0)); memset(env->pmsav8.mair1, 0, sizeof(env->pmsav8.mair1)); } diff --git a/target/arm/helper.c b/target/arm/helper.c index 5394cef..48e0fc6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2385,7 +2385,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const A= RMCPRegInfo *ri) return 0; } =20 - u32p +=3D env->pmsav7.rnr; + u32p +=3D env->pmsav7.rnr[M_REG_NS]; return *u32p; } =20 @@ -2399,7 +2399,7 @@ static void pmsav7_write(CPUARMState *env, const ARMC= PRegInfo *ri, return; } =20 - u32p +=3D env->pmsav7.rnr; + u32p +=3D env->pmsav7.rnr[M_REG_NS]; tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */ *u32p =3D value; } @@ -2442,7 +2442,7 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { .resetfn =3D arm_cp_reset_ignore }, { .name =3D "RGNR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 2, .= opc2 =3D 0, .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr), + .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), .writefn =3D pmsav7_rgnr_write, .resetfn =3D arm_cp_reset_ignore }, REGINFO_SENTINEL diff --git a/target/arm/machine.c b/target/arm/machine.c index 05c6c7a..6941e35 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -167,7 +167,7 @@ static bool pmsav7_rgnr_vmstate_validate(void *opaque, = int version_id) { ARMCPU *cpu =3D opaque; =20 - return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion; + return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion; } =20 static const VMStateDescription vmstate_pmsav7 =3D { @@ -205,7 +205,7 @@ static const VMStateDescription vmstate_pmsav7_rnr =3D { .minimum_version_id =3D 1, .needed =3D pmsav7_rnr_needed, .fields =3D (VMStateField[]) { - VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU), + VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU), VMSTATE_END_OF_LIST() } }; @@ -235,6 +235,13 @@ static const VMStateDescription vmstate_pmsav8 =3D { } }; =20 +static bool s_rnr_vmstate_validate(void *opaque, int version_id) +{ + ARMCPU *cpu =3D opaque; + + return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion; +} + static bool m_security_needed(void *opaque) { ARMCPU *cpu =3D opaque; @@ -261,6 +268,8 @@ static const VMStateDescription vmstate_m_security =3D { 0, vmstate_info_uint32, uint32_t), VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dre= gion, 0, vmstate_info_uint32, uint32_t), + VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), + VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate= ), VMSTATE_END_OF_LIST() } }; --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503416477065286.1607465152599; Tue, 22 Aug 2017 08:41:17 -0700 (PDT) Received: from localhost ([::1]:55486 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBIq-0001JO-0N for importer@patchew.org; Tue, 22 Aug 2017 11:41:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53443) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnr-0006Vn-En for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnp-0003FB-20 for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:15 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36974) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnl-0003Ah-LZ; Tue, 22 Aug 2017 11:09:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnk-0004jy-Mk; Tue, 22 Aug 2017 16:09:08 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:54 +0100 Message-Id: <1503414539-28762-16-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 15/20] target/arm: Make MPU_CTRL register banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the MPU_CTRL register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 9 +++++---- target/arm/helper.c | 5 +++-- target/arm/machine.c | 3 ++- 4 files changed, 11 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 43d36d6..78cd3f0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -429,7 +429,7 @@ typedef struct CPUARMState { uint32_t dfsr; /* Debug Fault Status Register */ uint32_t mmfar; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ - unsigned mpu_ctrl; /* MPU_CTRL */ + unsigned mpu_ctrl[2]; /* MPU_CTRL */ int exception; uint32_t primask[2]; uint32_t faultmask[2]; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index c3c214c..a4c298f 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -541,7 +541,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t, MemTxAttrs attrs) return cpu->pmsav7_dregion << 8; break; case 0xd94: /* MPU_CTRL */ - return cpu->env.v7m.mpu_ctrl; + return cpu->env.v7m.mpu_ctrl[attrs.secure]; case 0xd98: /* MPU_RNR */ return cpu->env.pmsav7.rnr[attrs.secure]; case 0xd9c: /* MPU_RBAR */ @@ -720,9 +720,10 @@ static void nvic_writel(NVICState *s, uint32_t offset,= uint32_t value, qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE= is " "UNPREDICTABLE\n"); } - cpu->env.v7m.mpu_ctrl =3D value & (R_V7M_MPU_CTRL_ENABLE_MASK | - R_V7M_MPU_CTRL_HFNMIENA_MASK | - R_V7M_MPU_CTRL_PRIVDEFENA_MASK); + cpu->env.v7m.mpu_ctrl[attrs.secure] + =3D value & (R_V7M_MPU_CTRL_ENABLE_MASK | + R_V7M_MPU_CTRL_HFNMIENA_MASK | + R_V7M_MPU_CTRL_PRIVDEFENA_MASK); tlb_flush(CPU(cpu)); break; case 0xd98: /* MPU_RNR */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 48e0fc6..4a2148c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7096,7 +7096,7 @@ static inline bool regime_translation_disabled(CPUARM= State *env, ARMMMUIdx mmu_idx) { if (arm_feature(env, ARM_FEATURE_M)) { - switch (env->v7m.mpu_ctrl & + switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] & (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK= )) { case R_V7M_MPU_CTRL_ENABLE_MASK: /* Enabled, but not for HardFault and NMI */ @@ -8256,7 +8256,8 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, } =20 if (arm_feature(env, ARM_FEATURE_M)) { - return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; + return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] + & R_V7M_MPU_CTRL_PRIVDEFENA_MASK; } else { return regime_sctlr(env, mmu_idx) & SCTLR_BR; } diff --git a/target/arm/machine.c b/target/arm/machine.c index 6941e35..5cc95e8 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -123,7 +123,7 @@ static const VMStateDescription vmstate_m =3D { VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), VMSTATE_UINT32(env.v7m.bfar, ARMCPU), - VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU), + VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), VMSTATE_INT32(env.v7m.exception, ARMCPU), VMSTATE_END_OF_LIST() }, @@ -270,6 +270,7 @@ static const VMStateDescription vmstate_m_security =3D { 0, vmstate_info_uint32, uint32_t), VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate= ), + VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503416685105988.1177127592185; Tue, 22 Aug 2017 08:44:45 -0700 (PDT) Received: from localhost ([::1]:55837 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBMB-00050f-J0 for importer@patchew.org; Tue, 22 Aug 2017 11:44:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53648) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnz-0006hE-23 for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnu-0003Kj-CX for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:23 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36962) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnn-00037y-Mj; Tue, 22 Aug 2017 11:09:11 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnl-0004kK-Cw; Tue, 22 Aug 2017 16:09:09 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:55 +0100 Message-Id: <1503414539-28762-17-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 16/20] target/arm: Make CCR register banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the CCR register banked if v8M security extensions are enabled. This is slightly more complicated than the other "add banking" patches because there is one bit in the register which is not banked. We keep the live data in the NS copy of the register, and adjust it on register reads and writes. (Since we don't currently implement the behaviour that the bit controls, there is nowhere else that needs to care.) This patch includes the enforcement of the bits which are newly RES1 in ARMv8M. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 36 ++++++++++++++++++++++++++++++------ target/arm/cpu.c | 12 +++++++++--- target/arm/helper.c | 5 +++-- target/arm/machine.c | 3 ++- 5 files changed, 45 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 78cd3f0..25ebf9e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -423,7 +423,7 @@ typedef struct CPUARMState { uint32_t vecbase[2]; uint32_t basepri[2]; uint32_t control[2]; - uint32_t ccr; /* Configuration and Control */ + uint32_t ccr[2]; /* Configuration and Control */ uint32_t cfsr; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index a4c298f..f071649 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -448,7 +448,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offs= et, MemTxAttrs attrs) /* TODO: Implement SLEEPONEXIT. */ return 0; case 0xd14: /* Configuration Control. */ - return cpu->env.v7m.ccr; + /* The BFHFNMIGN bit is the only non-banked bit; we + * keep it in the non-secure copy of the register. + */ + val =3D cpu->env.v7m.ccr[attrs.secure]; + val |=3D cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK; + return val; case 0xd24: /* System Handler Status. */ val =3D 0; if (s->vectors[ARMV7M_EXCP_MEM].active) { @@ -673,7 +678,23 @@ static void nvic_writel(NVICState *s, uint32_t offset,= uint32_t value, R_V7M_CCR_USERSETMPEND_MASK | R_V7M_CCR_NONBASETHRDENA_MASK); =20 - cpu->env.v7m.ccr =3D value; + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { + /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */ + value |=3D R_V7M_CCR_NONBASETHRDENA_MASK + | R_V7M_CCR_STKALIGN_MASK; + } + if (attrs.secure) { + /* the BFHFNMIGN bit is not banked; keep that in the NS copy */ + int new_bfhnmign =3D !!(value & R_V7M_CCR_BFHFNMIGN_MASK); + + cpu->env.v7m.ccr[M_REG_NS] =3D deposit32(cpu->env.v7m.ccr[M_RE= G_NS], + R_V7M_CCR_BFHFNMIGN_SH= IFT, + R_V7M_CCR_BFHFNMIGN_LE= NGTH, + new_bfhnmign); + value &=3D ~R_V7M_CCR_BFHFNMIGN_MASK; + } + + cpu->env.v7m.ccr[attrs.secure] =3D value; break; case 0xd24: /* System Handler Control. */ s->vectors[ARMV7M_EXCP_MEM].active =3D (value & (1 << 0)) !=3D 0; @@ -860,12 +881,15 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, } } =20 -static bool nvic_user_access_ok(NVICState *s, hwaddr offset) +static bool nvic_user_access_ok(NVICState *s, hwaddr offset, MemTxAttrs at= trs) { /* Return true if unprivileged access to this register is permitted. */ switch (offset) { case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */ - return s->cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK; + /* For access via STIR_NS it is the NS CCR.USERSETMPEND that + * controls access even though the CPU is in Secure state (I_QDKX). + */ + return s->cpu->env.v7m.ccr[attrs.secure] & R_V7M_CCR_USERSETMPEND_= MASK; default: /* All other user accesses cause a BusFault unconditionally */ return false; @@ -881,7 +905,7 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwadd= r addr, unsigned i, startvec, end; uint32_t val; =20 - if (attrs.user && !nvic_user_access_ok(s, addr)) { + if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { /* Generate BusFault for unprivileged accesses */ return MEMTX_ERROR; } @@ -971,7 +995,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwad= dr addr, =20 trace_nvic_sysreg_write(addr, value, size); =20 - if (attrs.user && !nvic_user_access_ok(s, addr)) { + if (attrs.user && !nvic_user_access_ok(s, addr, attrs)) { /* Generate BusFault for unprivileged accesses */ return MEMTX_ERROR; } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 11038b8..3c2ff11 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -189,11 +189,17 @@ static void arm_cpu_reset(CPUState *s) env->v7m.secure =3D true; } =20 - /* The reset value of this bit is IMPDEF, but ARM recommends + /* In v7M the reset value of this bit is IMPDEF, but ARM recommends * that it resets to 1, so QEMU always does that rather than making - * it dependent on CPU model. + * it dependent on CPU model. In v8M it is RES1. */ - env->v7m.ccr =3D R_V7M_CCR_STKALIGN_MASK; + env->v7m.ccr[M_REG_NS] =3D R_V7M_CCR_STKALIGN_MASK; + env->v7m.ccr[M_REG_S] =3D R_V7M_CCR_STKALIGN_MASK; + if (arm_feature(env, ARM_FEATURE_V8)) { + /* in v8M the NONBASETHRDENA bit [0] is RES1 */ + env->v7m.ccr[M_REG_NS] |=3D R_V7M_CCR_NONBASETHRDENA_MASK; + env->v7m.ccr[M_REG_S] |=3D R_V7M_CCR_NONBASETHRDENA_MASK; + } =20 /* Unlike A/R profile, M profile defines the reset LR value */ env->regs[14] =3D 0xffffffff; diff --git a/target/arm/helper.c b/target/arm/helper.c index 4a2148c..28b3d6c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6118,7 +6118,8 @@ static void v7m_push_stack(ARMCPU *cpu) uint32_t xpsr =3D xpsr_read(env); =20 /* Align stack pointer if the guest wants that */ - if ((env->regs[13] & 4) && (env->v7m.ccr & R_V7M_CCR_STKALIGN_MASK)) { + if ((env->regs[13] & 4) && + (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKALIGN_MASK)) { env->regs[13] -=3D 4; xpsr |=3D XPSR_SPREALIGN; } @@ -6216,7 +6217,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* fall through */ case 9: /* Return to Thread using Main stack */ if (!rettobase && - !(env->v7m.ccr & R_V7M_CCR_NONBASETHRDENA_MASK)) { + !(env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_NONBASETHRDENA_MAS= K)) { ufault =3D true; } break; diff --git a/target/arm/machine.c b/target/arm/machine.c index 5cc95e8..4457ec6 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -117,7 +117,7 @@ static const VMStateDescription vmstate_m =3D { VMSTATE_UINT32(env.v7m.vecbase[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), - VMSTATE_UINT32(env.v7m.ccr, ARMCPU), + VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), @@ -271,6 +271,7 @@ static const VMStateDescription vmstate_m_security =3D { VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU), VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate= ), VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503417769396276.41800105902666; Tue, 22 Aug 2017 09:02:49 -0700 (PDT) Received: from localhost ([::1]:57516 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBdg-0003n4-3X for importer@patchew.org; Tue, 22 Aug 2017 12:02:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53555) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAnw-0006dP-6K for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAns-0003JR-La for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:20 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36978) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnn-0003CS-Er; Tue, 22 Aug 2017 11:09:11 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnm-0004l3-5h; Tue, 22 Aug 2017 16:09:10 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:56 +0100 Message-Id: <1503414539-28762-18-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 17/20] target/arm: Make MMFAR banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the MMFAR register banked if v8M security extensions are enabled. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.h | 2 +- hw/intc/armv7m_nvic.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/machine.c | 3 ++- 4 files changed, 7 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 25ebf9e..21c68d7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -427,7 +427,7 @@ typedef struct CPUARMState { uint32_t cfsr; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ - uint32_t mmfar; /* MemManage Fault Address */ + uint32_t mmfar[2]; /* MemManage Fault Address */ uint32_t bfar; /* BusFault Address */ unsigned mpu_ctrl[2]; /* MPU_CTRL */ int exception; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index f071649..99b62ac 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -506,7 +506,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t, MemTxAttrs attrs) case 0xd30: /* Debug Fault Status. */ return cpu->env.v7m.dfsr; case 0xd34: /* MMFAR MemManage Fault Address */ - return cpu->env.v7m.mmfar; + return cpu->env.v7m.mmfar[attrs.secure]; case 0xd38: /* Bus Fault Address. */ return cpu->env.v7m.bfar; case 0xd3c: /* Aux Fault Status. */ @@ -723,7 +723,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, = uint32_t value, cpu->env.v7m.dfsr &=3D ~value; /* W1C */ break; case 0xd34: /* Mem Manage Address. */ - cpu->env.v7m.mmfar =3D value; + cpu->env.v7m.mmfar[attrs.secure] =3D value; return; case 0xd38: /* Bus Fault Address. */ cpu->env.v7m.bfar =3D value; diff --git a/target/arm/helper.c b/target/arm/helper.c index 28b3d6c..e587e85 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6380,10 +6380,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) case EXCP_DATA_ABORT: env->v7m.cfsr |=3D (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); - env->v7m.mmfar =3D env->exception.vaddress; + env->v7m.mmfar[env->v7m.secure] =3D env->exception.vaddres= s; qemu_log_mask(CPU_LOG_INT, "...with CFSR.DACCVIOL and MMFAR 0x%x\n", - env->v7m.mmfar); + env->v7m.mmfar[env->v7m.secure]); break; } armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM); diff --git a/target/arm/machine.c b/target/arm/machine.c index 4457ec6..5122e58 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -121,7 +121,7 @@ static const VMStateDescription vmstate_m =3D { VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), - VMSTATE_UINT32(env.v7m.mmfar, ARMCPU), + VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.bfar, ARMCPU), VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU), VMSTATE_INT32(env.v7m.exception, ARMCPU), @@ -272,6 +272,7 @@ static const VMStateDescription vmstate_m_security =3D { VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate= ), VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503416012587526.0365427524455; Tue, 22 Aug 2017 08:33:32 -0700 (PDT) Received: from localhost ([::1]:54651 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBBL-0001k0-8N for importer@patchew.org; Tue, 22 Aug 2017 11:33:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53745) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAo4-0006pq-83 for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAo2-0003QX-HH for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:28 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36984) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnp-0003E6-RH; Tue, 22 Aug 2017 11:09:14 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnn-0004lV-1q; Tue, 22 Aug 2017 16:09:11 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:57 +0100 Message-Id: <1503414539-28762-19-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 18/20] target/arm: Make CFSR register banked for v8M X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the CFSR register banked if v8M security extensions are enabled. Not all the bits in this register are banked: the BFSR bits [15:8] are shared between S and NS, and we store them in the NS copy of the register. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 7 ++++++- hw/intc/armv7m_nvic.c | 15 +++++++++++++-- target/arm/helper.c | 18 +++++++++--------- target/arm/machine.c | 3 ++- 4 files changed, 30 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 21c68d7..3683537 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -424,7 +424,7 @@ typedef struct CPUARMState { uint32_t basepri[2]; uint32_t control[2]; uint32_t ccr[2]; /* Configuration and Control */ - uint32_t cfsr; /* Configurable Fault Status */ + uint32_t cfsr[2]; /* Configurable Fault Status */ uint32_t hfsr; /* HardFault Status */ uint32_t dfsr; /* Debug Fault Status Register */ uint32_t mmfar[2]; /* MemManage Fault Address */ @@ -1210,6 +1210,11 @@ FIELD(V7M_CFSR, NOCP, 16 + 3, 1) FIELD(V7M_CFSR, UNALIGNED, 16 + 8, 1) FIELD(V7M_CFSR, DIVBYZERO, 16 + 9, 1) =20 +/* V7M CFSR bit masks covering all of the subregister bits */ +FIELD(V7M_CFSR, MMFSR, 0, 8) +FIELD(V7M_CFSR, BFSR, 8, 8) +FIELD(V7M_CFSR, UFSR, 16, 16) + /* V7M HFSR bits */ FIELD(V7M_HFSR, VECTTBL, 1, 1) FIELD(V7M_HFSR, FORCED, 30, 1) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 99b62ac..3c14cc8 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -500,7 +500,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offs= et, MemTxAttrs attrs) } return val; case 0xd28: /* Configurable Fault Status. */ - return cpu->env.v7m.cfsr; + /* The BFSR bits [15:8] are shared between security states + * and we store them in the NS copy + */ + val =3D cpu->env.v7m.cfsr[attrs.secure]; + val |=3D cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK; + return val; case 0xd2c: /* Hard Fault Status. */ return cpu->env.v7m.hfsr; case 0xd30: /* Debug Fault Status. */ @@ -714,7 +719,13 @@ static void nvic_writel(NVICState *s, uint32_t offset,= uint32_t value, nvic_irq_update(s); break; case 0xd28: /* Configurable Fault Status. */ - cpu->env.v7m.cfsr &=3D ~value; /* W1C */ + cpu->env.v7m.cfsr[attrs.secure] &=3D ~value; /* W1C */ + if (attrs.secure) { + /* The BFSR bits [15:8] are shared between security states + * and we store them in the NS copy. + */ + cpu->env.v7m.cfsr[M_REG_NS] &=3D ~(value & R_V7M_CFSR_BFSR_MAS= K); + } break; case 0xd2c: /* Hard Fault Status. */ cpu->env.v7m.hfsr &=3D ~value; /* W1C */ diff --git a/target/arm/helper.c b/target/arm/helper.c index e587e85..67b3874 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6229,7 +6229,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* Bad exception return: instead of popping the exception * stack, directly take a usage fault on the current stack. */ - env->v7m.cfsr |=3D R_V7M_CFSR_INVPC_MASK; + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); v7m_exception_taken(cpu, type | 0xf0000000); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " @@ -6271,7 +6271,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) if (return_to_handler !=3D arm_v7m_is_handler_mode(env)) { /* Take an INVPC UsageFault by pushing the stack again. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - env->v7m.cfsr |=3D R_V7M_CFSR_INVPC_MASK; + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; v7m_push_stack(cpu); v7m_exception_taken(cpu, type | 0xf0000000); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe= : " @@ -6330,15 +6330,15 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_UDEF: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - env->v7m.cfsr |=3D R_V7M_CFSR_UNDEFINSTR_MASK; + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_UNDEFINSTR_MASK; break; case EXCP_NOCP: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - env->v7m.cfsr |=3D R_V7M_CFSR_NOCP_MASK; + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_NOCP_MASK; break; case EXCP_INVSTATE: armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); - env->v7m.cfsr |=3D R_V7M_CFSR_INVSTATE_MASK; + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVSTATE_MASK; break; case EXCP_SWI: /* The PC already points to the next instruction. */ @@ -6354,11 +6354,11 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) case 0x8: /* External Abort */ switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: - env->v7m.cfsr |=3D R_V7M_CFSR_PRECISERR_MASK; + env->v7m.cfsr[M_REG_NS] |=3D R_V7M_CFSR_PRECISERR_MASK; qemu_log_mask(CPU_LOG_INT, "...with CFSR.PRECISERR\n"); break; case EXCP_DATA_ABORT: - env->v7m.cfsr |=3D + env->v7m.cfsr[M_REG_NS] |=3D (R_V7M_CFSR_IBUSERR_MASK | R_V7M_CFSR_BFARVALID_MASK); env->v7m.bfar =3D env->exception.vaddress; qemu_log_mask(CPU_LOG_INT, @@ -6374,11 +6374,11 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) */ switch (cs->exception_index) { case EXCP_PREFETCH_ABORT: - env->v7m.cfsr |=3D R_V7M_CFSR_IACCVIOL_MASK; + env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_IACCVIOL_MA= SK; qemu_log_mask(CPU_LOG_INT, "...with CFSR.IACCVIOL\n"); break; case EXCP_DATA_ABORT: - env->v7m.cfsr |=3D + env->v7m.cfsr[env->v7m.secure] |=3D (R_V7M_CFSR_DACCVIOL_MASK | R_V7M_CFSR_MMARVALID_MASK); env->v7m.mmfar[env->v7m.secure] =3D env->exception.vaddres= s; qemu_log_mask(CPU_LOG_INT, diff --git a/target/arm/machine.c b/target/arm/machine.c index 5122e58..3cc94b4 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -118,7 +118,7 @@ static const VMStateDescription vmstate_m =3D { VMSTATE_UINT32(env.v7m.basepri[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.control[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.ccr[M_REG_NS], ARMCPU), - VMSTATE_UINT32(env.v7m.cfsr, ARMCPU), + VMSTATE_UINT32(env.v7m.cfsr[M_REG_NS], ARMCPU), VMSTATE_UINT32(env.v7m.hfsr, ARMCPU), VMSTATE_UINT32(env.v7m.dfsr, ARMCPU), VMSTATE_UINT32(env.v7m.mmfar[M_REG_NS], ARMCPU), @@ -273,6 +273,7 @@ static const VMStateDescription vmstate_m_security =3D { VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.ccr[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.mmfar[M_REG_S], ARMCPU), + VMSTATE_UINT32(env.v7m.cfsr[M_REG_S], ARMCPU), VMSTATE_END_OF_LIST() } }; --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503417083463839.8028051463665; Tue, 22 Aug 2017 08:51:23 -0700 (PDT) Received: from localhost ([::1]:56536 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkBSc-0002QF-6b for importer@patchew.org; Tue, 22 Aug 2017 11:51:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53703) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAo1-0006lN-R4 for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAnt-0003KG-SP for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:25 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36984) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAno-0003E6-OL; Tue, 22 Aug 2017 11:09:12 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAnn-0004m0-Pn; Tue, 22 Aug 2017 16:09:11 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:58 +0100 Message-Id: <1503414539-28762-20-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 19/20] target/arm: Move regime_is_secure() to target/arm/internals.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move the regime_is_secure() utility function to internals.h; we are going to want to call it from translate.c. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/internals.h | 26 ++++++++++++++++++++++++++ target/arm/helper.c | 26 -------------------------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index bb06946..eb171b1 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -478,4 +478,30 @@ static inline void arm_call_el_change_hook(ARMCPU *cpu) } } =20 +/* Return true if this address translation regime is secure */ +static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) +{ + switch (mmu_idx) { + case ARMMMUIdx_S12NSE0: + case ARMMMUIdx_S12NSE1: + case ARMMMUIdx_S1NSE0: + case ARMMMUIdx_S1NSE1: + case ARMMMUIdx_S1E2: + case ARMMMUIdx_S2NS: + case ARMMMUIdx_MPriv: + case ARMMMUIdx_MNegPri: + case ARMMMUIdx_MUser: + return false; + case ARMMMUIdx_S1E3: + case ARMMMUIdx_S1SE0: + case ARMMMUIdx_S1SE1: + case ARMMMUIdx_MSPriv: + case ARMMMUIdx_MSNegPri: + case ARMMMUIdx_MSUser: + return true; + default: + g_assert_not_reached(); + } +} + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 67b3874..b1ae73c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7060,32 +7060,6 @@ static inline uint32_t regime_el(CPUARMState *env, A= RMMMUIdx mmu_idx) } } =20 -/* Return true if this address translation regime is secure */ -static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_S12NSE0: - case ARMMMUIdx_S12NSE1: - case ARMMMUIdx_S1NSE0: - case ARMMMUIdx_S1NSE1: - case ARMMMUIdx_S1E2: - case ARMMMUIdx_S2NS: - case ARMMMUIdx_MPriv: - case ARMMMUIdx_MNegPri: - case ARMMMUIdx_MUser: - return false; - case ARMMMUIdx_S1E3: - case ARMMMUIdx_S1SE0: - case ARMMMUIdx_S1SE1: - case ARMMMUIdx_MSPriv: - case ARMMMUIdx_MSNegPri: - case ARMMMUIdx_MSUser: - return true; - default: - g_assert_not_reached(); - } -} - /* Return the SCTLR value which controls this address translation regime */ static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) { --=20 2.7.4 From nobody Mon May 6 11:11:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1503415784063419.2973829157726; Tue, 22 Aug 2017 08:29:44 -0700 (PDT) Received: from localhost ([::1]:54441 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkB7e-000713-Ix for importer@patchew.org; Tue, 22 Aug 2017 11:29:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53731) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dkAo2-0006mo-VC for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dkAo1-0003Pc-B9 for qemu-devel@nongnu.org; Tue, 22 Aug 2017 11:09:26 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:36984) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dkAnq-0003E6-SR; Tue, 22 Aug 2017 11:09:15 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1dkAno-0004mp-Ir; Tue, 22 Aug 2017 16:09:12 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 22 Aug 2017 16:08:59 +0100 Message-Id: <1503414539-28762-21-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> References: <1503414539-28762-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 20/20] target/arm: Implement BXNS, and banked stack pointers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement the BXNS v8M instruction, which is like BX but will do a jump-and-switch-to-NonSecure if the branch target address has bit 0 clear. This is the first piece of code which implements "switch to the other security state", so the commit also includes the code to switch the stack pointers around, which is the only complicated part of switching security state. BLXNS is more complicated than just "BXNS but set the link register", so we leave it for a separate commit. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 13 +++++++++ target/arm/helper.h | 2 ++ target/arm/translate.h | 1 + target/arm/helper.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ target/arm/machine.c | 2 ++ target/arm/translate.c | 42 ++++++++++++++++++++++++++- 6 files changed, 138 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3683537..5e7b68b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -419,7 +419,20 @@ typedef struct CPUARMState { } cp15; =20 struct { + /* M profile has up to 4 stack pointers: + * a Main Stack Pointer and a Process Stack Pointer for each + * of the Secure and Non-Secure states. (If the CPU doesn't support + * the security extension then it has only two SPs.) + * In QEMU we always store the currently active SP in regs[13], + * and the non-active SP for the current security state in + * v7m.other_sp. The stack pointers for the inactive security state + * are stored in other_ss_msp and other_ss_psp. + * switch_v7m_security_state() is responsible for rearranging them + * when we change security state. + */ uint32_t other_sp; + uint32_t other_ss_msp; + uint32_t other_ss_psp; uint32_t vecbase[2]; uint32_t basepri[2]; uint32_t control[2]; diff --git a/target/arm/helper.h b/target/arm/helper.h index df86bf7..64afbac 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -63,6 +63,8 @@ DEF_HELPER_1(cpsr_read, i32, env) DEF_HELPER_3(v7m_msr, void, env, i32, i32) DEF_HELPER_2(v7m_mrs, i32, env, i32) =20 +DEF_HELPER_2(v7m_bxns, void, env, i32) + DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32) DEF_HELPER_3(set_cp_reg, void, env, ptr, i32) DEF_HELPER_2(get_cp_reg, i32, env, ptr) diff --git a/target/arm/translate.h b/target/arm/translate.h index 2fe144b..ef625ad 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -32,6 +32,7 @@ typedef struct DisasContext { int vec_len; int vec_stride; bool v7m_handler_mode; + bool v8m_secure; /* true if v8M and we're in Secure mode */ /* Immediate value in AArch32 SVC insn; must be set if is_jmp =3D=3D D= ISAS_SWI * so that top level loop can generate correct syndrome information. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index b1ae73c..4489bbd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5875,6 +5875,12 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t = reg) return 0; } =20 +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) +{ + /* translate.c should never generate calls here in user-only mode */ + g_assert_not_reached(); +} + void switch_mode(CPUARMState *env, int mode) { ARMCPU *cpu =3D arm_env_get_cpu(env); @@ -6049,6 +6055,18 @@ static uint32_t v7m_pop(CPUARMState *env) return val; } =20 +/* Return true if we're using the process stack pointer (not the MSP) */ +static bool v7m_using_psp(CPUARMState *env) +{ + /* Handler mode always uses the main stack; for thread mode + * the CONTROL.SPSEL bit determines the answer. + * Note that in v7M it is not possible to be in Handler mode with + * CONTROL.SPSEL non-zero, but in v8M it is, so we must check both. + */ + return !arm_v7m_is_handler_mode(env) && + env->v7m.control[env->v7m.secure] & R_V7M_CONTROL_SPSEL_MASK; +} + /* Switch to V7M main or process stack pointer. */ static void switch_v7m_sp(CPUARMState *env, bool new_spsel) { @@ -6067,6 +6085,67 @@ static void switch_v7m_sp(CPUARMState *env, bool new= _spsel) } } =20 +/* Switch M profile security state between NS and S */ +static void switch_v7m_security_state(CPUARMState *env, bool new_secstate) +{ + uint32_t new_ss_msp, new_ss_psp; + + if (env->v7m.secure =3D=3D new_secstate) { + return; + } + + /* All the banked state is accessed by looking at env->v7m.secure + * except for the stack pointer; rearrange the SP appropriately. + */ + new_ss_msp =3D env->v7m.other_ss_msp; + new_ss_psp =3D env->v7m.other_ss_psp; + + if (v7m_using_psp(env)) { + env->v7m.other_ss_psp =3D env->regs[13]; + env->v7m.other_ss_msp =3D env->v7m.other_sp; + } else { + env->v7m.other_ss_msp =3D env->regs[13]; + env->v7m.other_ss_psp =3D env->v7m.other_sp; + } + + env->v7m.secure =3D new_secstate; + + if (v7m_using_psp(env)) { + env->regs[13] =3D new_ss_psp; + env->v7m.other_sp =3D new_ss_msp; + } else { + env->regs[13] =3D new_ss_msp; + env->v7m.other_sp =3D new_ss_psp; + } +} + +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) +{ + /* Handle v7M BXNS: + * - if the return value is a magic value, do exception return (like = BX) + * - otherwise bit 0 of the return value is the target security state + */ + if (dest >=3D 0xff000000) { + /* This is an exception return magic value; put it where + * do_v7m_exception_exit() expects and raise EXCEPTION_EXIT. + * Note that if we ever add gen_ss_advance() singlestep support to + * M profile this should count as an "instruction execution comple= te" + * event (compare gen_bx_excret_final_code()). + */ + env->regs[15] =3D dest & ~1; + env->thumb =3D dest & 1; + HELPER(exception_internal)(env, EXCP_EXCEPTION_EXIT); + /* notreached */ + } + + /* translate.c should have made BXNS UNDEF unless we're secure */ + assert(env->v7m.secure); + + switch_v7m_security_state(env, dest & 1); + env->thumb =3D 1; + env->regs[15] =3D dest & ~1; +} + static uint32_t arm_v7m_load_vector(ARMCPU *cpu) { CPUState *cs =3D CPU(cpu); diff --git a/target/arm/machine.c b/target/arm/machine.c index 3cc94b4..1aca40d 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -257,6 +257,8 @@ static const VMStateDescription vmstate_m_security =3D { .needed =3D m_security_needed, .fields =3D (VMStateField[]) { VMSTATE_UINT32(env.v7m.secure, ARMCPU), + VMSTATE_UINT32(env.v7m.other_ss_msp, ARMCPU), + VMSTATE_UINT32(env.v7m.other_ss_psp, ARMCPU), VMSTATE_UINT32(env.v7m.basepri[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.primask[M_REG_S], ARMCPU), VMSTATE_UINT32(env.v7m.faultmask[M_REG_S], ARMCPU), diff --git a/target/arm/translate.c b/target/arm/translate.c index 6aa2d7c..e7966e2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -994,6 +994,25 @@ static inline void gen_bx_excret_final_code(DisasConte= xt *s) gen_exception_internal(EXCP_EXCEPTION_EXIT); } =20 +static inline void gen_bxns(DisasContext *s, int rm) +{ + TCGv_i32 var =3D load_reg(s, rm); + + /* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory + * we need to sync state before calling it, but: + * - we don't need to do gen_set_pc_im() because the bxns helper will + * always set the PC itself + * - we don't need to do gen_set_condexec() because BXNS is UNPREDICT= ABLE + * unless it's outside an IT block or the last insn in an IT block, + * so we know that condexec =3D=3D 0 (already set at the top of the= TB) + * is correct in the non-UNPREDICTABLE cases, and we can choose + * "zeroes the IT bits" as our UNPREDICTABLE behaviour otherwise. + */ + gen_helper_v7m_bxns(cpu_env, var); + tcg_temp_free_i32(var); + s->is_jmp =3D DISAS_EXIT; +} + /* Variant of store_reg which uses branch&exchange logic when storing to r15 in ARM architecture v7 and above. The source must be a temporary and will be marked as dead. */ @@ -11185,12 +11204,31 @@ static void disas_thumb_insn(CPUARMState *env, Di= sasContext *s) */ bool link =3D insn & (1 << 7); =20 - if (insn & 7) { + if (insn & 3) { goto undef; } if (link) { ARCH(5); } + if ((insn & 4)) { + /* BXNS/BLXNS: only exists for v8M with the + * security extensions, and always UNDEF if NonSecure. + * We don't implement these in the user-only mode + * either (in theory you can use them from Secure User + * mode but they are too tied in to system emulation.) + */ + if (!s->v8m_secure || IS_USER_ONLY) { + goto undef; + } + if (link) { + /* BLXNS: not yet implemented */ + goto undef; + } else { + gen_bxns(s, rm); + } + break; + } + /* BLX/BX */ tmp =3D load_reg(s, rm); if (link) { val =3D (uint32_t)s->pc | 1; @@ -11878,6 +11916,8 @@ void gen_intermediate_code(CPUState *cs, Translatio= nBlock *tb) dc->vec_stride =3D ARM_TBFLAG_VECSTRIDE(tb->flags); dc->c15_cpar =3D ARM_TBFLAG_XSCALE_CPAR(tb->flags); dc->v7m_handler_mode =3D ARM_TBFLAG_HANDLER(tb->flags); + dc->v8m_secure =3D arm_feature(env, ARM_FEATURE_M_SECURITY) && + regime_is_secure(env, dc->mmu_idx); dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; =20 --=20 2.7.4