From nobody Sat Apr 27 06:24:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1503013040206491.9854109811117; Thu, 17 Aug 2017 16:37:20 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1diUIy-0004Ct-7R; Fri, 18 Aug 2017 01:34:24 +0200 Received: from mail-lf0-f67.google.com ([209.85.215.67]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1diUIo-0004BR-LW for seabios@seabios.org; Fri, 18 Aug 2017 01:34:22 +0200 Received: by mail-lf0-f67.google.com with SMTP id x16so5260802lfb.4 for ; Thu, 17 Aug 2017 16:36:57 -0700 (PDT) Received: from localhost.localdomain ([93.185.28.201]) by smtp.gmail.com with ESMTPSA id y1sm903381lja.86.2017.08.17.16.36.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 17 Aug 2017 16:36:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=EOoQ+KUj10XCtwV66P/xX9bI5anyDN6ckJ7Mwh+l138=; b=XGvuEWJLBin6/ZkFrC2eQzsGGtmORMwqRCQSSg2QZLXe5wUkQJQ6l4F8oh49kGy4k2 v/IuvyczNh4iurPd9k4yfR0Hcq2zA82Glj7rw7eF/3Y6A8IRgivx/mUG3J6Xa8k5vYMp lU8JufLDYnrPueIMfGq9Hu4hhNYUbUeWchl1QQq1mSj8H136riGUa9hYny6sbBKJ8dmp AVrMiy4AQU4Tt+XaO54I4QyIGF7ZzZuQd4FZ4aH27wkYtbCwvnW9iXqFJnv8/kW3ku1P Xw98X+U2yz6nQhjmOqEUuOB8oRzE1XH1D8Bs8hKMM5Chbp5ScT0UAXT5wb1wpY706Gk7 EKYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=EOoQ+KUj10XCtwV66P/xX9bI5anyDN6ckJ7Mwh+l138=; b=OVapIu0CZy/v+PXSkXocjuX5X+xw2qr4VjHyxPtcY7svqR9a6Of7L9qKYf2voneEE8 8XCUWgugkCXZHv5LOltoqXSZ4VeWhgsUQi3BuhdY1WFVZjPdHQmOwuq1leJTfI+0150V a+s3POdUtG2N9HcpVpyX4YjAye9urWW4s+ZGB4+A12cWidvOE1YYfF2McxHX/vewIIq/ jg6ui3HYJNIBlR+6IaLJJEVyv+RtL5Sn88CfNXzOQIEm1IOAhgUAxfw63QWN2QJWJyN4 eCWl3G2ZmAGgEzYT+1jdn6UO+RZZuegepBlMYh8z8vWvCoJXRa5jSVt4CibVZ2EZNFfw DTPQ== X-Gm-Message-State: AHYfb5hvLCB4o245q+GIdEr7ij1TULiIIN2rUfI7MUK6JPUYM1AIptn1 Jc/Gj27G/ElyIA== X-Received: by 10.25.216.212 with SMTP id r81mr2282654lfi.26.1503013015857; Thu, 17 Aug 2017 16:36:55 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Fri, 18 Aug 2017 02:36:47 +0300 Message-Id: <1503013010-11500-2-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503013010-11500-1-git-send-email-zuban32s@gmail.com> References: <1503013010-11500-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -4.5 (----) Subject: [SeaBIOS] [PATCH v7 1/4] hw/pci: introduce pcie-pci-bridge device X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, seabios@seabios.org, lersek@redhat.com, mst@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Introduce a new PCIExpress-to-PCI Bridge device, which is a hot-pluggable PCI Express device and supports devices hot-plug with SHPC. This device is intended to replace the DMI-to-PCI Bridge. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- hw/pci-bridge/Makefile.objs | 2 +- hw/pci-bridge/pcie_pci_bridge.c | 192 ++++++++++++++++++++++++++++++++++++= ++++ include/hw/pci/pci.h | 1 + 3 files changed, 194 insertions(+), 1 deletion(-) create mode 100644 hw/pci-bridge/pcie_pci_bridge.c diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs index c4683cf..666db37 100644 --- a/hw/pci-bridge/Makefile.objs +++ b/hw/pci-bridge/Makefile.objs @@ -1,4 +1,4 @@ -common-obj-y +=3D pci_bridge_dev.o +common-obj-y +=3D pci_bridge_dev.o pcie_pci_bridge.o common-obj-$(CONFIG_PCIE_PORT) +=3D pcie_root_port.o gen_pcie_root_port.o common-obj-$(CONFIG_PXB) +=3D pci_expander_bridge.o common-obj-$(CONFIG_XIO3130) +=3D xio3130_upstream.o xio3130_downstream.o diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridg= e.c new file mode 100644 index 0000000..9aa5cc3 --- /dev/null +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -0,0 +1,192 @@ +/* + * QEMU Generic PCIE-PCI Bridge + * + * Copyright (c) 2017 Aleksandr Bezzubikov + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/msi.h" +#include "hw/pci/shpc.h" +#include "hw/pci/slotid_cap.h" + +typedef struct PCIEPCIBridge { + /*< private >*/ + PCIBridge parent_obj; + + OnOffAuto msi; + MemoryRegion shpc_bar; + /*< public >*/ +} PCIEPCIBridge; + +#define TYPE_PCIE_PCI_BRIDGE_DEV "pcie-pci-bridge" +#define PCIE_PCI_BRIDGE_DEV(obj) \ + OBJECT_CHECK(PCIEPCIBridge, (obj), TYPE_PCIE_PCI_BRIDGE_DEV) + +static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp) +{ + PCIBridge *br =3D PCI_BRIDGE(d); + PCIEPCIBridge *pcie_br =3D PCIE_PCI_BRIDGE_DEV(d); + int rc, pos; + + pci_bridge_initfn(d, TYPE_PCI_BUS); + + d->config[PCI_INTERRUPT_PIN] =3D 0x1; + memory_region_init(&pcie_br->shpc_bar, OBJECT(d), "shpc-bar", + shpc_bar_size(d)); + rc =3D shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0, errp); + if (rc) { + goto error; + } + + rc =3D pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, errp); + if (rc < 0) { + goto cap_error; + } + + pos =3D pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp); + if (pos < 0) { + goto pm_error; + } + d->exp.pm_cap =3D pos; + pci_set_word(d->config + pos + PCI_PM_PMC, 0x3); + + pcie_cap_arifwd_init(d); + pcie_cap_deverr_init(d); + + rc =3D pcie_aer_init(d, PCI_ERR_VER, 0x100, PCI_ERR_SIZEOF, errp); + if (rc < 0) { + goto aer_error; + } + + if (pcie_br->msi !=3D ON_OFF_AUTO_OFF) { + rc =3D msi_init(d, 0, 1, true, true, errp); + if (rc < 0) { + goto msi_error; + } + } + pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, &pcie_br->shpc_bar); + return; + +msi_error: + pcie_aer_exit(d); +aer_error: +pm_error: + pcie_cap_exit(d); +cap_error: + shpc_free(d); +error: + pci_bridge_exitfn(d); +} + +static void pcie_pci_bridge_exit(PCIDevice *d) +{ + PCIEPCIBridge *bridge_dev =3D PCIE_PCI_BRIDGE_DEV(d); + pcie_cap_exit(d); + shpc_cleanup(d, &bridge_dev->shpc_bar); + pci_bridge_exitfn(d); +} + +static void pcie_pci_bridge_reset(DeviceState *qdev) +{ + PCIDevice *d =3D PCI_DEVICE(qdev); + pci_bridge_reset(qdev); + msi_reset(d); + shpc_reset(d); +} + +static void pcie_pci_bridge_write_config(PCIDevice *d, + uint32_t address, uint32_t val, int len) +{ + pci_bridge_write_config(d, address, val, len); + msi_write_config(d, address, val, len); + shpc_cap_write_config(d, address, val, len); +} + +static Property pcie_pci_bridge_dev_properties[] =3D { + DEFINE_PROP_ON_OFF_AUTO("msi", PCIEPCIBridge, msi, ON_OFF_AUTO_ON), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription pcie_pci_bridge_dev_vmstate =3D { + .name =3D TYPE_PCIE_PCI_BRIDGE_DEV, + .fields =3D (VMStateField[]) { + VMSTATE_PCI_DEVICE(parent_obj, PCIBridge), + SHPC_VMSTATE(shpc, PCIDevice, NULL), + VMSTATE_END_OF_LIST() + } +}; + +static void pcie_pci_bridge_hotplug_cb(HotplugHandler *hotplug_dev, + DeviceState *dev, Error **errp) +{ + PCIDevice *pci_hotplug_dev =3D PCI_DEVICE(hotplug_dev); + + if (!shpc_present(pci_hotplug_dev)) { + error_setg(errp, "standard hotplug controller has been disabled fo= r " + "this %s", TYPE_PCIE_PCI_BRIDGE_DEV); + return; + } + shpc_device_hotplug_cb(hotplug_dev, dev, errp); +} + +static void pcie_pci_bridge_hot_unplug_request_cb(HotplugHandler *hotplug_= dev, + DeviceState *dev, + Error **errp) +{ + PCIDevice *pci_hotplug_dev =3D PCI_DEVICE(hotplug_dev); + + if (!shpc_present(pci_hotplug_dev)) { + error_setg(errp, "standard hotplug controller has been disabled fo= r " + "this %s", TYPE_PCIE_PCI_BRIDGE_DEV); + return; + } + shpc_device_hot_unplug_request_cb(hotplug_dev, dev, errp); +} + +static void pcie_pci_bridge_class_init(ObjectClass *klass, void *data) +{ + PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + HotplugHandlerClass *hc =3D HOTPLUG_HANDLER_CLASS(klass); + + k->is_express =3D 1; + k->is_bridge =3D 1; + k->vendor_id =3D PCI_VENDOR_ID_REDHAT; + k->device_id =3D PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE; + k->realize =3D pcie_pci_bridge_realize; + k->exit =3D pcie_pci_bridge_exit; + k->config_write =3D pcie_pci_bridge_write_config; + dc->vmsd =3D &pcie_pci_bridge_dev_vmstate; + dc->props =3D pcie_pci_bridge_dev_properties; + dc->vmsd =3D &pcie_pci_bridge_dev_vmstate; + dc->reset =3D &pcie_pci_bridge_reset; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + hc->plug =3D pcie_pci_bridge_hotplug_cb; + hc->unplug_request =3D pcie_pci_bridge_hot_unplug_request_cb; +} + +static const TypeInfo pcie_pci_bridge_info =3D { + .name =3D TYPE_PCIE_PCI_BRIDGE_DEV, + .parent =3D TYPE_PCI_BRIDGE, + .instance_size =3D sizeof(PCIEPCIBridge), + .class_init =3D pcie_pci_bridge_class_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_HOTPLUG_HANDLER }, + { }, + } +}; + +static void pciepci_register(void) +{ + type_register_static(&pcie_pci_bridge_info); +} + +type_init(pciepci_register); diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index e598b09..b33a34f 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -98,6 +98,7 @@ #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d +#define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e #define PCI_DEVICE_ID_REDHAT_QXL 0x0100 =20 #define FMT_PCIBUS PRIx64 --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Sat Apr 27 06:24:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; 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Thu, 17 Aug 2017 16:36:57 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Fri, 18 Aug 2017 02:36:48 +0300 Message-Id: <1503013010-11500-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503013010-11500-1-git-send-email-zuban32s@gmail.com> References: <1503013010-11500-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -6.4 (------) Subject: [SeaBIOS] [PATCH v7 2/4] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, seabios@seabios.org, lersek@redhat.com, mst@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridges may need some extra info about bus number, IO, memory and prefetchable memory to reserve. QEMU can provide this with a special vendor-specific PCI capability. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- hw/pci/pci_bridge.c | 46 +++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/pci/pci_bridge.h | 25 ++++++++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 720119b..17feae5 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -408,6 +408,52 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus= _name, br->bus_name =3D bus_name; } =20 + +int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, + uint32_t bus_reserve, uint64_t io_res= erve, + uint32_t mem_non_pref_reserve, + uint32_t mem_pref_32_reserve, + uint64_t mem_pref_64_reserve, + Error **errp) +{ + if (mem_pref_32_reserve !=3D (uint32_t)-1 && + mem_pref_64_reserve !=3D (uint64_t)-1) { + error_setg(errp, + "PCI resource reserve cap: PREF32 and PREF64 conflict"); + return -EINVAL; + } + + if (bus_reserve =3D=3D (uint32_t)-1 && + io_reserve =3D=3D (uint64_t)-1 && + mem_non_pref_reserve =3D=3D (uint32_t)-1 && + mem_pref_32_reserve =3D=3D (uint32_t)-1 && + mem_pref_64_reserve =3D=3D (uint64_t)-1) { + return 0; + } + + size_t cap_len =3D sizeof(PCIBridgeQemuCap); + PCIBridgeQemuCap cap =3D { + .len =3D cap_len, + .type =3D REDHAT_PCI_CAP_RESOURCE_RESERVE, + .bus_res =3D bus_reserve, + .io =3D io_reserve, + .mem =3D mem_non_pref_reserve, + .mem_pref_32 =3D mem_pref_32_reserve, + .mem_pref_64 =3D mem_pref_64_reserve + }; + + int offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, + cap_offset, cap_len, errp); + if (offset < 0) { + return offset; + } + + memcpy(dev->config + offset + PCI_CAP_FLAGS, + (char *)&cap + PCI_CAP_FLAGS, + cap_len - PCI_CAP_FLAGS); + return 0; +} + static const TypeInfo pci_bridge_type_info =3D { .name =3D TYPE_PCI_BRIDGE, .parent =3D TYPE_PCI_DEVICE, diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index ff7cbaa..1acadc2 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -67,4 +67,29 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_n= ame, #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ =20 +typedef struct PCIBridgeQemuCap { + uint8_t id; /* Standard PCI capability header field */ + uint8_t next; /* Standard PCI capability header field */ + uint8_t len; /* Standard PCI vendor-specific capability header fiel= d */ + uint8_t type; /* Red Hat vendor-specific capability type. + Types are defined with REDHAT_PCI_CAP_ prefix */ + + uint32_t bus_res; /* Minimum number of buses to reserve */ + uint64_t io; /* IO space to reserve */ + uint32_t mem; /* Non-prefetchable memory to reserve */ + /* At most one of the following two fields may be set to a value + * different from -1 */ + uint32_t mem_pref_32; /* Prefetchable memory to reserve (32-bit MMIO) = */ + uint64_t mem_pref_64; /* Prefetchable memory to reserve (64-bit MMIO) = */ +} PCIBridgeQemuCap; + +#define REDHAT_PCI_CAP_RESOURCE_RESERVE 1 + +int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, + uint32_t bus_reserve, uint64_t io_reserve, + uint32_t mem_non_pref_reserve, + uint32_t mem_pref_32_reserve, + uint64_t mem_pref_64_reserve, + Error **errp); + #endif /* QEMU_PCI_BRIDGE_H */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Sat Apr 27 06:24:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; 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Thu, 17 Aug 2017 16:36:58 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Fri, 18 Aug 2017 02:36:49 +0300 Message-Id: <1503013010-11500-4-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503013010-11500-1-git-send-email-zuban32s@gmail.com> References: <1503013010-11500-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -4.0 (----) Subject: [SeaBIOS] [PATCH v7 3/4] hw/pci: add QEMU-specific PCI capability to the Generic PCI Express Root Port X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, seabios@seabios.org, lersek@redhat.com, mst@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" To enable hotplugging of a newly created pcie-pci-bridge, we need to tell firmware (e.g. SeaBIOS) to reserve additional buses or IO/MEM/PREF space for pcie-root-port. Additional bus reservation allows us to hotplug pcie-pci-bridge into this r= oot port. The number of buses and IO/MEM/PREF space to reserve are provided to the de= vice via a corresponding property, and to the firmware via new PCI capability. The properties' default values are -1 to keep default behavior unchanged. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- hw/pci-bridge/gen_pcie_root_port.c | 36 ++++++++++++++++++++++++++++++++++= ++ include/hw/pci/pcie_port.h | 1 + 2 files changed, 37 insertions(+) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_ro= ot_port.c index cb694d6..ed03ffc 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -16,6 +16,8 @@ #include "hw/pci/pcie_port.h" =20 #define TYPE_GEN_PCIE_ROOT_PORT "pcie-root-port" +#define GEN_PCIE_ROOT_PORT(obj) \ + OBJECT_CHECK(GenPCIERootPort, (obj), TYPE_GEN_PCIE_ROOT_PORT) =20 #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1 @@ -26,6 +28,13 @@ typedef struct GenPCIERootPort { /*< public >*/ =20 bool migrate_msix; + + /* additional resources to reserve on firmware init */ + uint32_t bus_reserve; + uint64_t io_reserve; + uint64_t mem_reserve; + uint64_t pref32_reserve; + uint64_t pref64_reserve; } GenPCIERootPort; =20 static uint8_t gen_rp_aer_vector(const PCIDevice *d) @@ -60,6 +69,24 @@ static bool gen_rp_test_migrate_msix(void *opaque, int v= ersion_id) return rp->migrate_msix; } =20 +static void gen_rp_realize(DeviceState *dev, Error **errp) +{ + PCIDevice *d =3D PCI_DEVICE(dev); + GenPCIERootPort *grp =3D GEN_PCIE_ROOT_PORT(d); + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(d); + + rpc->parent_realize(dev, errp); + + int rc =3D pci_bridge_qemu_reserve_cap_init(d, 0, grp->bus_reserve, + grp->io_reserve, grp->mem_reserve, grp->pref32_reserve, + grp->pref64_reserve, errp); + + if (rc < 0) { + rpc->parent_class.exit(d); + return; + } +} + static const VMStateDescription vmstate_rp_dev =3D { .name =3D "pcie-root-port", .version_id =3D 1, @@ -78,6 +105,11 @@ static const VMStateDescription vmstate_rp_dev =3D { =20 static Property gen_rp_props[] =3D { DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true= ), + DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, bus_reserve, -1), + DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort, io_reserve, -1), + DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort, mem_reserve, -1), + DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort, pref32_reserve, -1= ), + DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, pref64_reserve, -1= ), DEFINE_PROP_END_OF_LIST() }; =20 @@ -92,6 +124,10 @@ static void gen_rp_dev_class_init(ObjectClass *klass, v= oid *data) dc->desc =3D "PCI Express Root Port"; dc->vmsd =3D &vmstate_rp_dev; dc->props =3D gen_rp_props; + + rpc->parent_realize =3D dc->realize; + dc->realize =3D gen_rp_realize; + rpc->aer_vector =3D gen_rp_aer_vector; rpc->interrupts_init =3D gen_rp_interrupts_init; rpc->interrupts_uninit =3D gen_rp_interrupts_uninit; diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 1333266..0736014 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -65,6 +65,7 @@ void pcie_chassis_del_slot(PCIESlot *s); =20 typedef struct PCIERootPortClass { PCIDeviceClass parent_class; + DeviceRealize parent_realize; =20 uint8_t (*aer_vector)(const PCIDevice *dev); int (*interrupts_init)(PCIDevice *dev, Error **errp); --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Sat Apr 27 06:24:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; 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Thu, 17 Aug 2017 16:37:00 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Fri, 18 Aug 2017 02:36:50 +0300 Message-Id: <1503013010-11500-5-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503013010-11500-1-git-send-email-zuban32s@gmail.com> References: <1503013010-11500-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -1.0 (-) Subject: [SeaBIOS] [PATCH v7 4/4] docs: update documentation considering PCIE-PCI bridge X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marcel@redhat.com, seabios@seabios.org, lersek@redhat.com, mst@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Laszlo Ersek Reviewed-by: Marcel Apfelbaum --- docs/pcie.txt | 49 ++++++++++---------- docs/pcie_pci_bridge.txt | 114 +++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 140 insertions(+), 23 deletions(-) create mode 100644 docs/pcie_pci_bridge.txt diff --git a/docs/pcie.txt b/docs/pcie.txt index 5bada24..76b85ec 100644 --- a/docs/pcie.txt +++ b/docs/pcie.txt @@ -46,7 +46,7 @@ Place only the following kinds of devices directly on the= Root Complex: (2) PCI Express Root Ports (ioh3420), for starting exclusively PCI Exp= ress hierarchies. =20 - (3) DMI-PCI Bridges (i82801b11-bridge), for starting legacy PCI + (3) PCI Express to PCI Bridge (pcie-pci-bridge), for starting legacy P= CI hierarchies. =20 (4) Extra Root Complexes (pxb-pcie), if multiple PCI Express Root Buses @@ -55,18 +55,18 @@ Place only the following kinds of devices directly on t= he Root Complex: pcie.0 bus -----------------------------------------------------------------------= ----- | | | | - ----------- ------------------ ------------------ -------------- - | PCI Dev | | PCIe Root Port | | DMI-PCI Bridge | | pxb-pcie | - ----------- ------------------ ------------------ -------------- + ----------- ------------------ ------------------- -------------- + | PCI Dev | | PCIe Root Port | | PCIe-PCI Bridge | | pxb-pcie | + ----------- ------------------ ------------------- -------------- =20 2.1.1 To plug a device into pcie.0 as a Root Complex Integrated Endpoint u= se: -device [,bus=3Dpcie.0] 2.1.2 To expose a new PCI Express Root Bus use: -device pxb-pcie,id=3Dpcie.1,bus_nr=3Dx[,numa_node=3Dy][,addr=3D= z] - Only PCI Express Root Ports and DMI-PCI bridges can be connected - to the pcie.1 bus: + PCI Express Root Ports and PCI Express to PCI bridges can be + connected to the pcie.1 bus: -device ioh3420,id=3Droot_port1[,bus=3Dpcie.1][,chassis=3Dx][,sl= ot=3Dy][,addr=3Dz] \ - -device i82801b11-bridge,id=3Ddmi_pci_bridge1,bus=3Dpcie.1 + -device pcie-pci-bridge,id=3Dpcie_pci_bridge1,bus=3Dpcie.1 =20 =20 2.2 PCI Express only hierarchy @@ -130,24 +130,24 @@ Notes: Legacy PCI devices can be plugged into pcie.0 as Integrated Endpoints, but, as mentioned in section 5, doing so means the legacy PCI device in question will be incapable of hot-unplugging. -Besides that use DMI-PCI Bridges (i82801b11-bridge) in combination -with PCI-PCI Bridges (pci-bridge) to start PCI hierarchies. +Besides that use PCI Express to PCI Bridges (pcie-pci-bridge) in +combination with PCI-PCI Bridges (pci-bridge) to start PCI hierarchies. =20 -Prefer flat hierarchies. For most scenarios a single DMI-PCI Bridge +Prefer flat hierarchies. For most scenarios a single PCI Express to PCI Br= idge (having 32 slots) and several PCI-PCI Bridges attached to it (each supporting also 32 slots) will support hundreds of legacy devices. -The recommendation is to populate one PCI-PCI Bridge under the DMI-PCI Bri= dge -until is full and then plug a new PCI-PCI Bridge... +The recommendation is to populate one PCI-PCI Bridge under the +PCI Express to PCI Bridge until is full and then plug a new PCI-PCI Bridge= ... =20 pcie.0 bus ---------------------------------------------- | | - ----------- ------------------ - | PCI Dev | | DMI-PCI BRIDGE | - ---------- ------------------ + ----------- ------------------- + | PCI Dev | | PCIe-PCI Bridge | + ----------- ------------------- | | ------------------ ------------------ - | PCI-PCI Bridge | | PCI-PCI Bridge | ... + | PCI-PCI Bridge | | PCI-PCI Bridge | ------------------ ------------------ | | ----------- ----------- @@ -157,11 +157,11 @@ until is full and then plug a new PCI-PCI Bridge... 2.3.1 To plug a PCI device into pcie.0 as an Integrated Endpoint use: -device [,bus=3Dpcie.0] 2.3.2 Plugging a PCI device into a PCI-PCI Bridge: - -device i82801b11-bridge,id=3Ddmi_pci_bridge1[,bus=3Dpcie.0] = \ - -device pci-bridge,id=3Dpci_bridge1,bus=3Ddmi_pci_bridge1[,chassis_n= r=3Dx][,addr=3Dy] \ + -device pcie-pci-bridge,id=3Dpcie_pci_bridge1[,bus=3Dpcie.0] \ + -device pci-bridge,id=3Dpci_bridge1,bus=3Dpcie_pci_bridge1[,chassis_= nr=3Dx][,addr=3Dy] \ -device ,bus=3Dpci_bridge1[,addr=3Dx] Note that 'addr' cannot be 0 unless shpc=3Doff parameter is passed to - the PCI Bridge. + the PCI Bridge/PCI Express to PCI Bridge. =20 3. IO space issues =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -219,14 +219,16 @@ do not support hot-plug, so any devices plugged into = Root Complexes cannot be hot-plugged/hot-unplugged: (1) PCI Express Integrated Endpoints (2) PCI Express Root Ports - (3) DMI-PCI Bridges + (3) PCI Express to PCI Bridges (4) pxb-pcie =20 Be aware that PCI Express Downstream Ports can't be hot-plugged into an existing PCI Express Upstream Port. =20 -PCI devices can be hot-plugged into PCI-PCI Bridges. The PCI hot-plug is A= CPI -based and can work side by side with the PCI Express native hot-plug. +PCI devices can be hot-plugged into PCI Express to PCI and PCI-PCI Bridges. +The PCI hot-plug into PCI-PCI bridge is ACPI based, whereas hot-plug into +PCI Express to PCI bridges is SHPC-based. They both can work side by side = with +the PCI Express native hot-plug. =20 PCI Express devices can be natively hot-plugged/hot-unplugged into/from PCI Express Root Ports (and PCI Express Downstream Ports). @@ -234,10 +236,11 @@ PCI Express Root Ports (and PCI Express Downstream Po= rts). 5.1 Planning for hot-plug: (1) PCI hierarchy Leave enough PCI-PCI Bridge slots empty or add one - or more empty PCI-PCI Bridges to the DMI-PCI Bridge. + or more empty PCI-PCI Bridges to the PCI Express to PCI Bridge. =20 For each such PCI-PCI Bridge the Guest Firmware is expected to res= erve 4K IO space and 2M MMIO range to be used for all devices behind it. + Appropriate PCI capability is designed, see pcie_pci_bridge.txt. =20 Because of the hard IO limit of around 10 PCI Bridges (~ 40K space) per system don't use more than 9 PCI-PCI Bridges, leaving 4K for t= he diff --git a/docs/pcie_pci_bridge.txt b/docs/pcie_pci_bridge.txt new file mode 100644 index 0000000..5a4203f --- /dev/null +++ b/docs/pcie_pci_bridge.txt @@ -0,0 +1,114 @@ +Generic PCI Express to PCI Bridge +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +Description +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +PCIE-to-PCI bridge is a new method for legacy PCI +hierarchies creation on Q35 machines. + +Previously Intel DMI-to-PCI bridge was used for this purpose. +But due to its strict limitations - no support of hot-plug, +no cross-platform and cross-architecture support - a new generic +PCIE-to-PCI bridge should now be used for any legacy PCI device usage +with PCI Express machine. + +This generic PCIE-PCI bridge is a cross-platform device, +can be hot-plugged into appropriate root port (requires additional actions, +see 'PCIE-PCI bridge hot-plug' section), +and supports devices hot-plug into the bridge itself +(with some limitations, see below). + +Hot-plug of legacy PCI devices into the bridge +is provided by bridge's built-in Standard hot-plug Controller. +Though it still has some limitations, see below. + +PCIE-PCI bridge hot-plug +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Guest OSes require extra efforts to enable PCIE-PCI bridge hot-plug. +Motivation - now on init any PCI Express root port which doesn't have +any device plugged in, has no free buses reserved to provide any of them +to a hot-plugged devices in future. + +To solve this problem we reserve additional buses on a firmware level. +Currently only SeaBIOS is supported. +The way of bus number to reserve delivery is special +Red Hat vendor-specific PCI capability, added to the root port +that is planned to have PCIE-PCI bridge hot-plugged in. + +Capability layout (defined in include/hw/pci/pci_bridge.h): + + uint8_t id; Standard PCI capability header field + uint8_t next; Standard PCI capability header field + uint8_t len; Standard PCI vendor-specific capability header field + + uint8_t type; Red Hat vendor-specific capability type + List of currently existing types: + RESOURCE_RESERVE =3D 1 + + + uint32_t bus_res; Minimum number of buses to reserve + + uint64_t io; IO space to reserve + uint32_t mem Non-prefetchable memory to reserve + + At most one of the following two fields may be set to a value + different from -1: + uint32_t mem_pref_32; Prefetchable memory to reserve (32-bit MMIO) + uint64_t mem_pref_64; Prefetchable memory to reserve (64-bit MMIO) + +If any reservation field is -1 then this kind of reservation is not +needed and must be ignored by firmware. + +At the moment this capability is used only in QEMU generic PCIe root port +(-device pcie-root-port). Capability construction function takes all reser= vation +fields values from corresponding device properties. By default all of them= are +set to -1 to leave root port's default behavior unchanged. + +Usage +=3D=3D=3D=3D=3D +A detailed command line would be: + +[qemu-bin + storage options] \ +-m 2G \ +-device pcie-root-port,bus=3Dpcie.0,id=3Drp1 \ +-device pcie-root-port,bus=3Dpcie.0,id=3Drp2 \ +-device pcie-root-port,bus=3Dpcie.0,id=3Drp3,bus-reserve=3D1 \ +-device pcie-pci-bridge,id=3Dbr1,bus=3Drp1 \ +-device pcie-pci-bridge,id=3Dbr2,bus=3Drp2 \ +-device e1000,bus=3Dbr1,addr=3D8 + +Then in monitor it's OK to execute next commands: +device_add pcie-pci-bridge,id=3Dbr3,bus=3Drp3 \ +device_add e1000,bus=3Dbr2,addr=3D1 \ +device_add e1000,bus=3Dbr3,addr=3D1 + +Here you have: + (1) Cold-plugged: + - Root ports: 1 QEMU generic root port with the capability mentioned a= bove, + 2 QEMU generic root ports without this capability; + - 2 PCIE-PCI bridges plugged into 2 different root ports; + - e1000 plugged into the first bridge. + (2) Hot-plugged: + - PCIE-PCI bridge, plugged into QEMU generic root port; + - 2 e1000 cards, one plugged into the cold-plugged PCIE-PCI bridge, + another plugged into the hot-plugged bridge. + +Limitations +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The PCIE-PCI bridge can be hot-plugged only into pcie-root-port that +has proper 'bus-reserve' property value to provide secondary bus for the +hot-plugged bridge. + +Windows 7 and older versions don't support hot-plug devices into the PCIE-= PCI bridge. +To enable device hot-plug into the bridge on Linux there're 3 ways: +1) Build shpchp module with this patch http://www.spinics.net/lists/linux-= pci/msg63052.html +2) Use kernel 4.14+ where the patch mentioned above is already merged. +3) Set 'msi' property to off - this forces the bridge to use legacy INTx, + which allows the bridge to notify the OS about hot-plug event without = having + BUSMASTER set. + +Implementation +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The PCIE-PCI bridge is based on PCI-PCI bridge, but also accumulates PCI E= xpress +features as a PCI Express device (is_express=3D1). + --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios