From nobody Tue Apr 30 03:57:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1503012842344901.9196457888016; Thu, 17 Aug 2017 16:34:02 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1diUFh-0003aB-7A; Fri, 18 Aug 2017 01:31:01 +0200 Received: from mail-lf0-f67.google.com ([209.85.215.67]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1diUFS-0003Wl-PA for seabios@seabios.org; Fri, 18 Aug 2017 01:30:59 +0200 Received: by mail-lf0-f67.google.com with SMTP id x16so5258217lfb.4 for ; Thu, 17 Aug 2017 16:33:29 -0700 (PDT) Received: from localhost.localdomain ([93.185.28.201]) by smtp.gmail.com with ESMTPSA id 96sm925433ljb.60.2017.08.17.16.33.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 17 Aug 2017 16:33:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N6+V7wnmbRAwAyThDHQGh8df4VtbF490wcd0LLsG958=; b=K78emfFwtj9maMlVgGlTaphclb66y1zcGHkET+KhyGPmtMDP+Hi+34hOvw/8oWX9aN xLcdDmy1LT4guVHN5ecwqP470yNBgcZNImIOYR2lzMpJWLJ9YlAdRFRYkAwbIFlc2J53 0+W9eA116nMrMcymEB9N067PmgUOKIjAUvL+F1BkhLJ5icLEkxp9VTJmtRqN7lWA34Ye 9smK4jKwDCkp+5w/2H06u8ciT8WrkCZb92Z1D+1qKvtkLGBxntLUjtLd9ssq6thLVNgC L4pOAxdRtaOwUqS3Hsjbh52VyMpDB1KAftMrTFS/WIfp/xR/smrKKq4+7xsJ2/fB/2lQ 18UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N6+V7wnmbRAwAyThDHQGh8df4VtbF490wcd0LLsG958=; b=QPh4diiHX78Nnm8ZtX8XAvMqm4Hb7A4ozofFuHcjoIrMRGSV/D6r6lu1NXSzmPJcza +087HUtBqiGBeAwKCprN2N0yLEZiqW2xjFXbxeir61b8G0pFk0Nk7bSFz5Gi1FbKBLEW dPdFliR7bdBy5ZwHVDtzCJrWg2zt7k29dCfO/CPY2HMWzBlnOdYTaEIT7y5vjyfEnSDl yZGXZ/o0Y0uagqV4e1gBTw+GmRFzEwod8tQMdRZVyP9Sw5EuzvE0eGExXo6UKuJWSt+B 3EWPs1SNCP5fi7XwoYBkuj2IAdwI/vYD9b9ryJsU7ZavZmHQM8ziQ7A8sJHV0Jq50qq0 yV3Q== X-Gm-Message-State: AHYfb5gZELTtGFrSX9ftWy3RPkfYBPyVFgED8O1EFvOGlYJ+y7VlXw66 F0py9mqE4yGBU7JjSD4= X-Received: by 10.25.143.214 with SMTP id s83mr2591632lfk.93.1503012807642; Thu, 17 Aug 2017 16:33:27 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Fri, 18 Aug 2017 02:33:19 +0300 Message-Id: <1503012801-10855-2-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503012801-10855-1-git-send-email-zuban32s@gmail.com> References: <1503012801-10855-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -4.5 (----) Subject: [SeaBIOS] [PATCH RESEND v7 1/3] pci: refactor pci_find_capapibilty to get bdf as the first argument instead of the whole pci_device X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Refactor pci_find_capability function to get bdf instead of a whole pci_device* as the only necessary field for this function is still bdf. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- src/fw/pciinit.c | 4 ++-- src/hw/pci.c | 25 +++++++++++++++++++++++++ src/hw/pci.h | 1 + src/hw/pcidevice.c | 24 ------------------------ src/hw/pcidevice.h | 1 - src/hw/virtio-pci.c | 6 +++--- 6 files changed, 31 insertions(+), 30 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 08221e6..864954f 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -762,7 +762,7 @@ static int pci_bus_hotplug_support(struct pci_bus *bus,= u8 pcie_cap) return downstream_port && slot_implemented; } =20 - shpc_cap =3D pci_find_capability(bus->bus_dev, PCI_CAP_ID_SHPC, 0); + shpc_cap =3D pci_find_capability(bus->bus_dev->bdf, PCI_CAP_ID_SHPC, 0= ); return !!shpc_cap; } =20 @@ -844,7 +844,7 @@ static int pci_bios_check_devices(struct pci_bus *busse= s) */ parent =3D &busses[0]; int type; - u8 pcie_cap =3D pci_find_capability(s->bus_dev, PCI_CAP_ID_EXP, 0); + u8 pcie_cap =3D pci_find_capability(s->bus_dev->bdf, PCI_CAP_ID_EX= P, 0); int hotplug_support =3D pci_bus_hotplug_support(s, pcie_cap); for (type =3D 0; type < PCI_REGION_TYPE_COUNT; type++) { u64 align =3D (type =3D=3D PCI_REGION_TYPE_IO) ? diff --git a/src/hw/pci.c b/src/hw/pci.c index 8e3d617..50d9d2d 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -58,6 +58,30 @@ pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on) pci_config_writew(bdf, addr, val); } =20 +u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap) +{ + int i; + u16 status =3D pci_config_readw(bdf, PCI_STATUS); + + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + if (cap =3D=3D 0) { + /* find first */ + cap =3D pci_config_readb(bdf, PCI_CAPABILITY_LIST); + } else { + /* find next */ + cap =3D pci_config_readb(bdf, cap + PCI_CAP_LIST_NEXT); + } + for (i =3D 0; cap && i <=3D 0xff; i++) { + if (pci_config_readb(bdf, cap + PCI_CAP_LIST_ID) =3D=3D cap_id) + return cap; + cap =3D pci_config_readb(bdf, cap + PCI_CAP_LIST_NEXT); + } + + return 0; +} + // Helper function for foreachbdf() macro - return next device int pci_next(int bdf, int bus) @@ -107,3 +131,4 @@ pci_reboot(void) outb(v|6, PORT_PCI_REBOOT); /* Actually do the reset */ udelay(50); } + diff --git a/src/hw/pci.h b/src/hw/pci.h index ee6e196..2e30e28 100644 --- a/src/hw/pci.h +++ b/src/hw/pci.h @@ -39,6 +39,7 @@ u32 pci_config_readl(u16 bdf, u32 addr); u16 pci_config_readw(u16 bdf, u32 addr); u8 pci_config_readb(u16 bdf, u32 addr); void pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on); +u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap); int pci_next(int bdf, int bus); int pci_probe_host(void); void pci_reboot(void); diff --git a/src/hw/pcidevice.c b/src/hw/pcidevice.c index cfebf66..8853cf7 100644 --- a/src/hw/pcidevice.c +++ b/src/hw/pcidevice.c @@ -134,30 +134,6 @@ pci_find_init_device(const struct pci_device_id *ids, = void *arg) return NULL; } =20 -u8 pci_find_capability(struct pci_device *pci, u8 cap_id, u8 cap) -{ - int i; - u16 status =3D pci_config_readw(pci->bdf, PCI_STATUS); - - if (!(status & PCI_STATUS_CAP_LIST)) - return 0; - - if (cap =3D=3D 0) { - /* find first */ - cap =3D pci_config_readb(pci->bdf, PCI_CAPABILITY_LIST); - } else { - /* find next */ - cap =3D pci_config_readb(pci->bdf, cap + PCI_CAP_LIST_NEXT); - } - for (i =3D 0; cap && i <=3D 0xff; i++) { - if (pci_config_readb(pci->bdf, cap + PCI_CAP_LIST_ID) =3D=3D cap_i= d) - return cap; - cap =3D pci_config_readb(pci->bdf, cap + PCI_CAP_LIST_NEXT); - } - - return 0; -} - // Enable PCI bus-mastering (ie, DMA) support on a pci device void pci_enable_busmaster(struct pci_device *pci) diff --git a/src/hw/pcidevice.h b/src/hw/pcidevice.h index 354b549..225d545 100644 --- a/src/hw/pcidevice.h +++ b/src/hw/pcidevice.h @@ -69,7 +69,6 @@ int pci_init_device(const struct pci_device_id *ids , struct pci_device *pci, void *arg); struct pci_device *pci_find_init_device(const struct pci_device_id *ids , void *arg); -u8 pci_find_capability(struct pci_device *pci, u8 cap_id, u8 cap); void pci_enable_busmaster(struct pci_device *pci); u16 pci_enable_iobar(struct pci_device *pci, u32 addr); void *pci_enable_membar(struct pci_device *pci, u32 addr); diff --git a/src/hw/virtio-pci.c b/src/hw/virtio-pci.c index e5c2c33..96f9c6b 100644 --- a/src/hw/virtio-pci.c +++ b/src/hw/virtio-pci.c @@ -19,7 +19,7 @@ #include "malloc.h" // free #include "output.h" // dprintf #include "pci.h" // pci_config_readl -#include "pcidevice.h" // pci_find_capability +#include "pcidevice.h" // struct pci_device #include "pci_regs.h" // PCI_BASE_ADDRESS_0 #include "string.h" // memset #include "virtio-pci.h" @@ -381,7 +381,7 @@ fail: =20 void vp_init_simple(struct vp_device *vp, struct pci_device *pci) { - u8 cap =3D pci_find_capability(pci, PCI_CAP_ID_VNDR, 0); + u8 cap =3D pci_find_capability(pci->bdf, PCI_CAP_ID_VNDR, 0); struct vp_cap *vp_cap; const char *mode; u32 offset, base, mul; @@ -479,7 +479,7 @@ void vp_init_simple(struct vp_device *vp, struct pci_de= vice *pci) vp_cap->cap, type, vp_cap->bar, addr, offset, mode); } =20 - cap =3D pci_find_capability(pci, PCI_CAP_ID_VNDR, cap); + cap =3D pci_find_capability(pci->bdf, PCI_CAP_ID_VNDR, cap); } =20 if (vp->common.cap && vp->notify.cap && vp->isr.cap && vp->device.cap)= { --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Tue Apr 30 03:57:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1503012857071731.4645352896143; Thu, 17 Aug 2017 16:34:17 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1diUFi-0003aO-4o; Fri, 18 Aug 2017 01:31:02 +0200 Received: from mail-lf0-f66.google.com ([209.85.215.66]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1diUFU-0003Wo-Hq for seabios@seabios.org; Fri, 18 Aug 2017 01:31:00 +0200 Received: by mail-lf0-f66.google.com with SMTP id w199so5253662lff.2 for ; Thu, 17 Aug 2017 16:33:31 -0700 (PDT) Received: from localhost.localdomain ([93.185.28.201]) by smtp.gmail.com with ESMTPSA id 96sm925433ljb.60.2017.08.17.16.33.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 17 Aug 2017 16:33:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JkYh3oQ9fyVfBf1WCfQknt9ahHGwgKu5WzdZIV13rjI=; b=r2dZFwSQCC3ZLHrNYwb6V/P6fml6154gV7t/vlil3tOfmCWoSdnH6vtsd6GwtNXKH7 bye7k2P3wHYM8H45U/P9gSN2/q8KnLXpmUM/+Ik4TD64/5TkG2jxDGMuaXNnI0LNd+74 zP0IPdkOVWt3HLE06QdmTqUedSJZeu80Ezk4alRDk39RuHkSjkRcUkit6jYZIJHd1TBm pOFML8gXjWjou+hzqvrgthaH0O1ilyOyOesBl3LhhG4+F2ipr9Wp92y9FydhK9lKvT+a Kxa/rVwZINzN9PdDjwJovA5VPB7d9IIygfgpTJt7ZEE7y6Ejnkvat7iDl+DfMFA98VQb 0tMg== X-Google-DKIM-Signature: v=1; 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Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red Hat PCI bridges, i.e. QEMU cooperation. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- src/fw/dev-pci.h | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 src/fw/dev-pci.h diff --git a/src/fw/dev-pci.h b/src/fw/dev-pci.h new file mode 100644 index 0000000..0dc5556 --- /dev/null +++ b/src/fw/dev-pci.h @@ -0,0 +1,53 @@ +#ifndef _PCI_CAP_H +#define _PCI_CAP_H + +#include "types.h" + +/* + * + * QEMU-specific vendor(Red Hat)-specific capability. + * It's intended to provide some hints for firmware to init PCI devices. + * + * Its structure is shown below: + * + * Header: + * + * u8 id; Standard PCI Capability Header field + * u8 next; Standard PCI Capability Header field + * u8 len; Standard PCI Capability Header field + * u8 type; Red Hat vendor-specific capability type + * Data: + * + * u32 bus_res; minimum bus number to reserve; + * this is necessary for PCI Express Root Ports + * to support PCI bridges hotplug + * u64 io; IO space to reserve + * u32 mem; non-prefetchable memory to reserve + * + * At most of the following two fields may be set to a value + * different from 0xFF...F: + * u32 prefetchable_mem_32; prefetchable memory to reserve (32-bit MMI= O) + * u64 prefetchable_mem_64; prefetchable memory to reserve (64-bit MMI= O) + * + * If any field value in Data section is 0xFF...F, + * it means that such kind of reservation is not needed and must be ignore= d. + * +*/ + +/* Offset of vendor-specific capability type field */ +#define PCI_CAP_REDHAT_TYPE_OFFSET 3 + +/* List of valid Red Hat vendor-specific capability types */ +#define REDHAT_CAP_RESOURCE_RESERVE 1 + + +/* Offsets of RESOURCE_RESERVE capability fields */ +#define RES_RESERVE_BUS_RES 4 +#define RES_RESERVE_IO 8 +#define RES_RESERVE_MEM 16 +#define RES_RESERVE_PREF_MEM_32 20 +#define RES_RESERVE_PREF_MEM_64 24 +#define RES_RESERVE_CAP_SIZE 32 + +#endif /* _PCI_CAP_H */ + --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Tue Apr 30 03:57:10 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; 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Thu, 17 Aug 2017 16:33:31 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Fri, 18 Aug 2017 02:33:21 +0300 Message-Id: <1503012801-10855-4-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1503012801-10855-1-git-send-email-zuban32s@gmail.com> References: <1503012801-10855-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -4.5 (----) Subject: [SeaBIOS] [PATCH RESEND v7 3/3] pci: enable RedHat PCI bridges to reserve additional resources on PCI init X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In case of Red Hat Generic PCIE Root Port reserve additional buses and/or IO/MEM/PREF space, which values are provided in a vendor-specific ca= pability. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- src/fw/pciinit.c | 106 +++++++++++++++++++++++++++++++++++++++++++++++++++= +--- src/hw/pci_ids.h | 3 ++ 2 files changed, 105 insertions(+), 4 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 864954f..7f0e439 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -15,6 +15,7 @@ #include "hw/pcidevice.h" // pci_probe_devices #include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL #include "hw/pci_regs.h" // PCI_COMMAND +#include "fw/dev-pci.h" // REDHAT_CAP_RESOURCE_RESERVE #include "list.h" // struct hlist_node #include "malloc.h" // free #include "output.h" // dprintf @@ -522,6 +523,32 @@ static void pci_bios_init_platform(void) } } =20 +static u8 pci_find_resource_reserve_capability(u16 bdf) +{ + if (pci_config_readw(bdf, PCI_VENDOR_ID) =3D=3D PCI_VENDOR_ID_REDHAT && + pci_config_readw(bdf, PCI_DEVICE_ID) =3D=3D + PCI_DEVICE_ID_REDHAT_ROOT_PORT) { + u8 cap =3D 0; + do { + cap =3D pci_find_capability(bdf, PCI_CAP_ID_VNDR, cap); + } while (cap && + pci_config_readb(bdf, cap + PCI_CAP_REDHAT_TYPE_OFFSET) != =3D + REDHAT_CAP_RESOURCE_RESERVE); + if (cap) { + u8 cap_len =3D pci_config_readb(bdf, cap + PCI_CAP_FLAGS); + if (cap_len < RES_RESERVE_CAP_SIZE) { + dprintf(1, "PCI: QEMU resource reserve cap length %d is in= valid\n", + cap_len); + } + } else { + dprintf(1, "PCI: invalid QEMU resource reserve cap offset\n"); + } + return cap; + } else { + dprintf(1, "PCI: QEMU resource reserve cap not found\n"); + return 0; + } +} =20 /**************************************************************** * Bus initialization @@ -578,9 +605,33 @@ pci_bios_init_bus_rec(int bus, u8 *pci_bus) pci_bios_init_bus_rec(secbus, pci_bus); =20 if (subbus !=3D *pci_bus) { + u8 res_bus =3D *pci_bus; + u8 cap =3D pci_find_resource_reserve_capability(bdf); + + if (cap) { + u32 tmp_res_bus =3D pci_config_readl(bdf, + cap + RES_RESERVE_BUS_RES); + if (tmp_res_bus !=3D (u32)-1) { + res_bus =3D tmp_res_bus & 0xFF; + if ((u8)(res_bus + secbus) < secbus || + (u8)(res_bus + secbus) < res_bus) { + dprintf(1, "PCI: bus_reserve value %d is invalid\n= ", + res_bus); + res_bus =3D 0; + } + } + if (secbus + res_bus > *pci_bus) { + dprintf(1, "PCI: QEMU resource reserve cap: bus =3D %u= \n", + res_bus); + res_bus =3D secbus + res_bus; + } else { + res_bus =3D *pci_bus; + } + } dprintf(1, "PCI: subordinate bus =3D 0x%x -> 0x%x\n", - subbus, *pci_bus); - subbus =3D *pci_bus; + subbus, res_bus); + subbus =3D res_bus; + *pci_bus =3D res_bus; } else { dprintf(1, "PCI: subordinate bus =3D 0x%x\n", subbus); } @@ -844,20 +895,67 @@ static int pci_bios_check_devices(struct pci_bus *bus= ses) */ parent =3D &busses[0]; int type; - u8 pcie_cap =3D pci_find_capability(s->bus_dev->bdf, PCI_CAP_ID_EX= P, 0); + u16 bdf =3D s->bus_dev->bdf; + u8 pcie_cap =3D pci_find_capability(bdf, PCI_CAP_ID_EXP, 0); + u8 qemu_cap =3D pci_find_resource_reserve_capability(bdf); + int hotplug_support =3D pci_bus_hotplug_support(s, pcie_cap); for (type =3D 0; type < PCI_REGION_TYPE_COUNT; type++) { u64 align =3D (type =3D=3D PCI_REGION_TYPE_IO) ? PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN; if (!pci_bridge_has_region(s->bus_dev, type)) continue; + u64 size =3D 0; + if (qemu_cap) { + u32 tmp_size; + u64 tmp_size_64; + switch(type) { + case PCI_REGION_TYPE_IO: + tmp_size_64 =3D (pci_config_readl(bdf, qemu_cap + RES_= RESERVE_IO) | + (u64)pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_IO + 4) << 32); + if (tmp_size_64 !=3D (u64)-1) { + size =3D tmp_size_64; + } + break; + case PCI_REGION_TYPE_MEM: + tmp_size =3D pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_MEM); + if (tmp_size !=3D (u32)-1) { + size =3D tmp_size; + } + break; + case PCI_REGION_TYPE_PREFMEM: + tmp_size =3D pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_PREF_MEM_32); + tmp_size_64 =3D (pci_config_readl(bdf, qemu_cap + RES_= RESERVE_PREF_MEM_64) | + (u64)pci_config_readl(bdf, qemu_cap + RES_RESE= RVE_PREF_MEM_64 + 4) << 32); + if (tmp_size !=3D (u32)-1 && tmp_size_64 =3D=3D (u64)-= 1) { + size =3D tmp_size; + } else if (tmp_size =3D=3D (u32)-1 && tmp_size_64 !=3D= (u64)-1) { + size =3D tmp_size_64; + } else if (tmp_size !=3D (u32)-1 && tmp_size_64 !=3D (= u64)-1) { + dprintf(1, "PCI: resource reserve cap PREF32 and P= REF64" + " conflict\n"); + } + break; + default: + break; + } + } if (pci_region_align(&s->r[type]) > align) align =3D pci_region_align(&s->r[type]); u64 sum =3D pci_region_sum(&s->r[type]); int resource_optional =3D pcie_cap && (type =3D=3D PCI_REGION_= TYPE_IO); if (!sum && hotplug_support && !resource_optional) sum =3D align; /* reserve min size for hot-plug */ - u64 size =3D ALIGN(sum, align); + if (size > sum) { + dprintf(1, "PCI: QEMU resource reserve cap: " + "size %08llx type %s\n", + size, region_type_name[type]); + if (type !=3D PCI_REGION_TYPE_IO) { + size =3D ALIGN(size, align); + } + } else { + size =3D ALIGN(sum, align); + } int is64 =3D pci_bios_bridge_region_is64(&s->r[type], s->bus_dev, type); // entry->bar is -1 if the entry represents a bridge region diff --git a/src/hw/pci_ids.h b/src/hw/pci_ids.h index 4ac73b4..38fa2ca 100644 --- a/src/hw/pci_ids.h +++ b/src/hw/pci_ids.h @@ -2263,6 +2263,9 @@ #define PCI_DEVICE_ID_KORENIX_JETCARDF0 0x1600 #define PCI_DEVICE_ID_KORENIX_JETCARDF1 0x16ff =20 +#define PCI_VENDOR_ID_REDHAT 0x1b36 +#define PCI_DEVICE_ID_REDHAT_ROOT_PORT 0x000C + #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 =20 --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios