From nobody Mon Feb 9 11:32:27 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1502121458471578.3571729131852; Mon, 7 Aug 2017 08:57:38 -0700 (PDT) Received: from localhost ([::1]:38125 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dekPR-0003Q2-9U for importer@patchew.org; Mon, 07 Aug 2017 11:57:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57485) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dekKT-0007xo-8q for qemu-devel@nongnu.org; Mon, 07 Aug 2017 11:52:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dekKO-0005nI-Ha for qemu-devel@nongnu.org; Mon, 07 Aug 2017 11:52:29 -0400 Received: from mel.act-europe.fr ([194.98.77.210]:54226 helo=smtp.eu.adacore.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dekKO-0005mT-Bq; Mon, 07 Aug 2017 11:52:24 -0400 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 6154E81362; Mon, 7 Aug 2017 17:52:23 +0200 (CEST) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DohHUu2vYBfe; Mon, 7 Aug 2017 17:52:23 +0200 (CEST) Received: from localhost.localdomain.localdomain (unknown [IPv6:2a01:e35:87f0:3180:2b18:7e65:c33:7f62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id DA6C58135E; Mon, 7 Aug 2017 17:52:22 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at eu.adacore.com From: KONRAD Frederic To: david@gibson.dropbear.id.au, agraf@suse.de Date: Mon, 7 Aug 2017 17:50:46 +0200 Message-Id: <1502121048-1816-3-git-send-email-frederic.konrad@adacore.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1502121048-1816-1-git-send-email-frederic.konrad@adacore.com> References: <1502121048-1816-1-git-send-email-frederic.konrad@adacore.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 194.98.77.210 Subject: [Qemu-devel] [PATCH for-2.11 2/4] booke206: fix tlbnps for fixed size TLB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: frederic.konrad@adacore.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some OS don't populate the TSIZE field when using a fixed size TLB which re= sult in a 1KB TLB. When the TLB is a fixed size TLB the TSIZE field should be ignored. Fix this wrong behavior with MAV 2.0. Signed-off-by: KONRAD Frederic --- target/ppc/cpu.h | 22 ++++++++++++++++++++++ target/ppc/mmu_helper.c | 16 ++++++++++------ 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index d2faea9..32a44a8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2490,6 +2490,28 @@ static inline uint32_t booke206_tlbnps(CPUPPCState *= env, const int tlbn) return ret; } =20 +static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tl= bn, + ppcmas_tlb_t *tlb) +{ + uint8_t i; + int32_t tsize =3D -1; + + for (i =3D 0; i < 32; i++) { + if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) { + if (tsize =3D=3D -1) { + tsize =3D i; + } else { + return; + } + } + } + + /* TLBnPS unimplemented? Odd.. */ + assert(tsize !=3D -1); + tlb->mas1 &=3D ~MAS1_TSIZE_MASK; + tlb->mas1 |=3D ((uint32_t)tsize) << MAS1_TSIZE_SHIFT; +} + #endif =20 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr) diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index f06b938..2a1f990 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -2632,12 +2632,16 @@ void helper_booke206_tlbwe(CPUPPCState *env) env->spr[SPR_BOOKE_MAS3]; tlb->mas1 =3D env->spr[SPR_BOOKE_MAS1]; =20 - /* MAV 1.0 only */ - if (!(tlbncfg & TLBnCFG_AVAIL)) { - /* force !AVAIL TLB entries to correct page size */ - tlb->mas1 &=3D ~MAS1_TSIZE_MASK; - /* XXX can be configured in MMUCSR0 */ - tlb->mas1 |=3D (tlbncfg & TLBnCFG_MINSIZE) >> 12; + if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) =3D=3D MMUCFG_MAVN_V2) { + /* For TLB which has a fixed size TSIZE is ignored with MAV2 */ + booke206_fixed_size_tlbn(env, tlbn, tlb); + } else { + if (!(tlbncfg & TLBnCFG_AVAIL)) { + /* force !AVAIL TLB entries to correct page size */ + tlb->mas1 &=3D ~MAS1_TSIZE_MASK; + /* XXX can be configured in MMUCSR0 */ + tlb->mas1 |=3D (tlbncfg & TLBnCFG_MINSIZE) >> 12; + } } =20 /* Make a mask from TLB size to discard invalid bits in EPN field */ --=20 1.8.3.1