From nobody Sun Apr 28 11:31:33 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 15019650305841004.0038146147596; Sat, 5 Aug 2017 13:30:30 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1de5ft-0004qE-Eg; Sat, 05 Aug 2017 22:27:53 +0200 Received: from mail-lf0-f68.google.com ([209.85.215.68]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1de5fk-0004ng-E2 for seabios@seabios.org; Sat, 05 Aug 2017 22:27:51 +0200 Received: by mail-lf0-f68.google.com with SMTP id t128so3080340lff.3 for ; Sat, 05 Aug 2017 13:30:07 -0700 (PDT) Received: from localhost.localdomain (broadband-109-173-19-108.moscow.rt.ru. [109.173.19.108]) by smtp.gmail.com with ESMTPSA id 79sm1952439ljf.8.2017.08.05.13.30.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 Aug 2017 13:30:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=N6+V7wnmbRAwAyThDHQGh8df4VtbF490wcd0LLsG958=; b=IOEkkbVnP2SkHHZXVaWbMDX5u9/oKsI+E6U2+3lI4icWT7av6DuTwzRWpgJC7KnjIX cUcPMNeNyGMpvF3duSZEVW2dT3f71BLa7DeuTt6YdK69WtnbSPKk7OT26/l1kKJjrJP1 1gwkxxgUwjApmCRSTyDZcqMpbQ71SJzxVzoYPB0PJU/NDqRll00tO/QtbkaU7ld0FeoD bMV8Rgk8P12jMSWo9hmmzayN453gBntE8pECnxoPPzqdJUXPjxHtkXPWpBR01PnbsRZF q/zvE5MO7CMVJKCo6rnRTuz3eraKlj+W3KPFxQQDK5UfE2OuPpfABERnprxF7VqP+wG6 aFdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=N6+V7wnmbRAwAyThDHQGh8df4VtbF490wcd0LLsG958=; b=W7TxWedzSiP+Y7p3iY5HHEXDj6F65luL1wiSbfImIteeZDdTA0UO7zguf63Tel9ohS gUVEIxWaBLvJxaoYujq1I13mtYxSXpRN8qaDPAd3HFGnCer2YgRmmStKwdqPuQ3BX66l KRFwA563xU9BgSZkulLTugONDpOWWs3iV35ZPs3WAYyFR9SvjxeEseBW2oaYRBt6i8s+ n20GUvKqtGZU6McyxL4Qu2tbOsWViyfkCtRBGhP9LhftdZ2xXV0sI9dGp6xRSFHZWdX+ XDKjHyWiuIEV9oYk9TrcOilvsk/+xqoLLBg7gQNeYEOd4TUSPtn4uFk+kMCvl9igg3Sp jGzQ== X-Gm-Message-State: AIVw110RY3B5VzgDj+lKhWwxBXy/VbZgPWemr4wTCB1/wVmPXAAxZRGv n97HlEWYTktVwyqLbtw= X-Received: by 10.46.83.80 with SMTP id t16mr2247886ljd.118.1501965005174; Sat, 05 Aug 2017 13:30:05 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Sat, 5 Aug 2017 23:29:52 +0300 Message-Id: <1501964994-5257-2-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501964994-5257-1-git-send-email-zuban32s@gmail.com> References: <1501964994-5257-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -3.5 (---) Subject: [SeaBIOS] [PATCH v4 1/3] pci: refactor pci_find_capapibilty to get bdf as the first argument instead of the whole pci_device X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Refactor pci_find_capability function to get bdf instead of a whole pci_device* as the only necessary field for this function is still bdf. Signed-off-by: Aleksandr Bezzubikov Reviewed-by: Marcel Apfelbaum --- src/fw/pciinit.c | 4 ++-- src/hw/pci.c | 25 +++++++++++++++++++++++++ src/hw/pci.h | 1 + src/hw/pcidevice.c | 24 ------------------------ src/hw/pcidevice.h | 1 - src/hw/virtio-pci.c | 6 +++--- 6 files changed, 31 insertions(+), 30 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 08221e6..864954f 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -762,7 +762,7 @@ static int pci_bus_hotplug_support(struct pci_bus *bus,= u8 pcie_cap) return downstream_port && slot_implemented; } =20 - shpc_cap =3D pci_find_capability(bus->bus_dev, PCI_CAP_ID_SHPC, 0); + shpc_cap =3D pci_find_capability(bus->bus_dev->bdf, PCI_CAP_ID_SHPC, 0= ); return !!shpc_cap; } =20 @@ -844,7 +844,7 @@ static int pci_bios_check_devices(struct pci_bus *busse= s) */ parent =3D &busses[0]; int type; - u8 pcie_cap =3D pci_find_capability(s->bus_dev, PCI_CAP_ID_EXP, 0); + u8 pcie_cap =3D pci_find_capability(s->bus_dev->bdf, PCI_CAP_ID_EX= P, 0); int hotplug_support =3D pci_bus_hotplug_support(s, pcie_cap); for (type =3D 0; type < PCI_REGION_TYPE_COUNT; type++) { u64 align =3D (type =3D=3D PCI_REGION_TYPE_IO) ? diff --git a/src/hw/pci.c b/src/hw/pci.c index 8e3d617..50d9d2d 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -58,6 +58,30 @@ pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on) pci_config_writew(bdf, addr, val); } =20 +u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap) +{ + int i; + u16 status =3D pci_config_readw(bdf, PCI_STATUS); + + if (!(status & PCI_STATUS_CAP_LIST)) + return 0; + + if (cap =3D=3D 0) { + /* find first */ + cap =3D pci_config_readb(bdf, PCI_CAPABILITY_LIST); + } else { + /* find next */ + cap =3D pci_config_readb(bdf, cap + PCI_CAP_LIST_NEXT); + } + for (i =3D 0; cap && i <=3D 0xff; i++) { + if (pci_config_readb(bdf, cap + PCI_CAP_LIST_ID) =3D=3D cap_id) + return cap; + cap =3D pci_config_readb(bdf, cap + PCI_CAP_LIST_NEXT); + } + + return 0; +} + // Helper function for foreachbdf() macro - return next device int pci_next(int bdf, int bus) @@ -107,3 +131,4 @@ pci_reboot(void) outb(v|6, PORT_PCI_REBOOT); /* Actually do the reset */ udelay(50); } + diff --git a/src/hw/pci.h b/src/hw/pci.h index ee6e196..2e30e28 100644 --- a/src/hw/pci.h +++ b/src/hw/pci.h @@ -39,6 +39,7 @@ u32 pci_config_readl(u16 bdf, u32 addr); u16 pci_config_readw(u16 bdf, u32 addr); u8 pci_config_readb(u16 bdf, u32 addr); void pci_config_maskw(u16 bdf, u32 addr, u16 off, u16 on); +u8 pci_find_capability(u16 bdf, u8 cap_id, u8 cap); int pci_next(int bdf, int bus); int pci_probe_host(void); void pci_reboot(void); diff --git a/src/hw/pcidevice.c b/src/hw/pcidevice.c index cfebf66..8853cf7 100644 --- a/src/hw/pcidevice.c +++ b/src/hw/pcidevice.c @@ -134,30 +134,6 @@ pci_find_init_device(const struct pci_device_id *ids, = void *arg) return NULL; } =20 -u8 pci_find_capability(struct pci_device *pci, u8 cap_id, u8 cap) -{ - int i; - u16 status =3D pci_config_readw(pci->bdf, PCI_STATUS); - - if (!(status & PCI_STATUS_CAP_LIST)) - return 0; - - if (cap =3D=3D 0) { - /* find first */ - cap =3D pci_config_readb(pci->bdf, PCI_CAPABILITY_LIST); - } else { - /* find next */ - cap =3D pci_config_readb(pci->bdf, cap + PCI_CAP_LIST_NEXT); - } - for (i =3D 0; cap && i <=3D 0xff; i++) { - if (pci_config_readb(pci->bdf, cap + PCI_CAP_LIST_ID) =3D=3D cap_i= d) - return cap; - cap =3D pci_config_readb(pci->bdf, cap + PCI_CAP_LIST_NEXT); - } - - return 0; -} - // Enable PCI bus-mastering (ie, DMA) support on a pci device void pci_enable_busmaster(struct pci_device *pci) diff --git a/src/hw/pcidevice.h b/src/hw/pcidevice.h index 354b549..225d545 100644 --- a/src/hw/pcidevice.h +++ b/src/hw/pcidevice.h @@ -69,7 +69,6 @@ int pci_init_device(const struct pci_device_id *ids , struct pci_device *pci, void *arg); struct pci_device *pci_find_init_device(const struct pci_device_id *ids , void *arg); -u8 pci_find_capability(struct pci_device *pci, u8 cap_id, u8 cap); void pci_enable_busmaster(struct pci_device *pci); u16 pci_enable_iobar(struct pci_device *pci, u32 addr); void *pci_enable_membar(struct pci_device *pci, u32 addr); diff --git a/src/hw/virtio-pci.c b/src/hw/virtio-pci.c index e5c2c33..96f9c6b 100644 --- a/src/hw/virtio-pci.c +++ b/src/hw/virtio-pci.c @@ -19,7 +19,7 @@ #include "malloc.h" // free #include "output.h" // dprintf #include "pci.h" // pci_config_readl -#include "pcidevice.h" // pci_find_capability +#include "pcidevice.h" // struct pci_device #include "pci_regs.h" // PCI_BASE_ADDRESS_0 #include "string.h" // memset #include "virtio-pci.h" @@ -381,7 +381,7 @@ fail: =20 void vp_init_simple(struct vp_device *vp, struct pci_device *pci) { - u8 cap =3D pci_find_capability(pci, PCI_CAP_ID_VNDR, 0); + u8 cap =3D pci_find_capability(pci->bdf, PCI_CAP_ID_VNDR, 0); struct vp_cap *vp_cap; const char *mode; u32 offset, base, mul; @@ -479,7 +479,7 @@ void vp_init_simple(struct vp_device *vp, struct pci_de= vice *pci) vp_cap->cap, type, vp_cap->bar, addr, offset, mode); } =20 - cap =3D pci_find_capability(pci, PCI_CAP_ID_VNDR, cap); + cap =3D pci_find_capability(pci->bdf, PCI_CAP_ID_VNDR, cap); } =20 if (vp->common.cap && vp->notify.cap && vp->isr.cap && vp->device.cap)= { --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Sun Apr 28 11:31:33 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 1501965037444257.9799007878445; Sat, 5 Aug 2017 13:30:37 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1de5g0-0004t1-Vh; Sat, 05 Aug 2017 22:28:01 +0200 Received: from mail-lf0-f66.google.com ([209.85.215.66]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1de5fl-0004oF-UC for seabios@seabios.org; Sat, 05 Aug 2017 22:27:58 +0200 Received: by mail-lf0-f66.google.com with SMTP id o85so3074398lff.1 for ; Sat, 05 Aug 2017 13:30:08 -0700 (PDT) Received: from localhost.localdomain (broadband-109-173-19-108.moscow.rt.ru. [109.173.19.108]) by smtp.gmail.com with ESMTPSA id 79sm1952439ljf.8.2017.08.05.13.30.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 Aug 2017 13:30:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4mMVWnBPq5mOMACHoyRiBI8DfjN/qdoD551A0y8uexo=; b=aMxG6YsXpn6ioOFKsBiOu2W2rrJiAnhKMMfklnrXudDintRlfubngRxMTK5WCK78Re hYPPqAxGkmeUyWtXspyNWUw4dIwePYYjYO/w8MSvD+wRFbPpY20j47vcj+a/y6v300rw fBzdxrtRxyqUnZrUA0v9QDM9qM3PgWqXbgS5qADplryMgajAJ5zmxawznc+akJJp7nyN 4SqWlI1DiXLqXqVUXhEa3OF/GxLrmLB5nNVRX5h+d+igd5EYq/76jPHlj7c/0ydTrsm7 StnhLbDkHIuj6x4tkWlMpz1gJWw1PKXSBe5T6E1BJJSMUvlLuJUPTrNX0EhKYBqaoQt3 mOUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4mMVWnBPq5mOMACHoyRiBI8DfjN/qdoD551A0y8uexo=; b=taOcGppD2qxNghBUYvOitVHB7RSKgGY0IsBZZmDptqRoAks3+9psXFCvsH4p3NT/xW JsX0HxT5Wsg39zjkXDXcG5o9vLwJkYVG93ojO0mlcaWjBFSiCVwwTk5Um7Mn0pGSXLX5 rmwdhxJA+qwi9rwW06Oc5I97fMPStblDa6FdxqdEGHQSOmnqH3c3pBvL3pIi0xTQbdJp u+MSWScd7j3LTMrTpZI7Cx03ClpdaOhDsg/TC2HDhohITjJLuL4uXQUyloOAOwFXwd8F zuKGHtDvjOHqw1cvvwBSzlm3oiJYS7QFx56Mk8ECSoQhfnlq8yFzcSwNWjtYZ0h8yt9U uP4w== X-Gm-Message-State: AHYfb5iQyckM+Yezy1jcp4BrwAxR5zW+qwWMROzU/7XKsdokP1lYqM6X 8jnXJvdrQ82zdyrgaNw= X-Received: by 10.46.14.9 with SMTP id 9mr2224984ljo.26.1501965006734; Sat, 05 Aug 2017 13:30:06 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Sat, 5 Aug 2017 23:29:53 +0300 Message-Id: <1501964994-5257-3-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501964994-5257-1-git-send-email-zuban32s@gmail.com> References: <1501964994-5257-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -2.6 (--) Subject: [SeaBIOS] [PATCH v4 2/3] pci: add QEMU-specific PCI capability structure X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridge devices may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. This capability is intended to be used only for Red Hat PCI bridges, i.e. QEMU cooperation. Signed-off-by: Aleksandr Bezzubikov --- src/fw/dev-pci.h | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 src/fw/dev-pci.h diff --git a/src/fw/dev-pci.h b/src/fw/dev-pci.h new file mode 100644 index 0000000..2c8ddb0 --- /dev/null +++ b/src/fw/dev-pci.h @@ -0,0 +1,50 @@ +#ifndef _PCI_CAP_H +#define _PCI_CAP_H + +#include "types.h" + +/* + +QEMU-specific vendor(Red Hat)-specific capability. +It's intended to provide some hints for firmware to init PCI devices. + +Its structure is shown below: + +Header: + +u8 id; Standard PCI Capability Header field +u8 next; Standard PCI Capability Header field +u8 len; Standard PCI Capability Header field +u8 type; Red Hat vendor-specific capability type: + now only REDHAT_CAP_TYP_QEMU=3D1 exists +Data: + +u32 bus_res; minimum bus number to reserve; + this is necessary for PCI Express Root Ports + to support PCIE-to-PCI bridge hotplug +u64 io; IO space to reserve +u64 mem; non-prefetchable memory space to reserve +u64 prefetchable_mem; prefetchable memory space to reserve + +If any field value in Data section is -1, +it means that such kind of reservation +is not needed and must be ignored. + +*/ + +/* Offset of vendor-specific capability type field */ +#define PCI_CAP_REDHAT_TYPE 3 + +/* List of valid Red Hat vendor-specific capability types */ +#define REDHAT_CAP_TYPE_QEMU 1 + + +/* Offsets of QEMU capability fields */ +#define QEMU_PCI_CAP_BUS_RES 4 +#define QEMU_PCI_CAP_LIMITS_OFFSET 8 +#define QEMU_PCI_CAP_IO 8 +#define QEMU_PCI_CAP_MEM 16 +#define QEMU_PCI_CAP_PREF_MEM 24 +#define QEMU_PCI_CAP_SIZE 32 + +#endif /* _PCI_CAP_H */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios From nobody Sun Apr 28 11:31:33 2024 Delivered-To: importer@patchew.org Received-SPF: none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) client-ip=80.81.252.135; envelope-from=seabios-bounces@seabios.org; helo=mail.coreboot.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 80.81.252.135 is neither permitted nor denied by domain of seabios.org) smtp.mailfrom=seabios-bounces@seabios.org Return-Path: Received: from mail.coreboot.org (mail.coreboot.org [80.81.252.135]) by mx.zohomail.com with SMTPS id 150196503710610.128561156033129; Sat, 5 Aug 2017 13:30:37 -0700 (PDT) Received: from [127.0.0.1] (helo=ra.coresystems.de) by mail.coreboot.org with esmtp (Exim 4.86_2) (envelope-from ) id 1de5g1-0004tD-Kt; Sat, 05 Aug 2017 22:28:01 +0200 Received: from mail-lf0-f65.google.com ([209.85.215.65]) by mail.coreboot.org with esmtps (TLSv1.2:ECDHE-RSA-AES128-GCM-SHA256:128) (Exim 4.86_2) (envelope-from ) id 1de5fn-0004oQ-9D for seabios@seabios.org; Sat, 05 Aug 2017 22:27:58 +0200 Received: by mail-lf0-f65.google.com with SMTP id w199so3069249lff.2 for ; Sat, 05 Aug 2017 13:30:09 -0700 (PDT) Received: from localhost.localdomain (broadband-109-173-19-108.moscow.rt.ru. [109.173.19.108]) by smtp.gmail.com with ESMTPSA id 79sm1952439ljf.8.2017.08.05.13.30.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 05 Aug 2017 13:30:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b/FueGBlYNAFQ/RajAwMkRjKV4N3VX+Jcw4nXuRvfOs=; b=Lzh516GSwtrD6nGHGK/bZvK5U/ErfQcgvc1WSasnKJInC/G0gLcMtK681OqWOs0SZF SVZdn61C3Og9TtsQ0lriVwIQhKg78Q3DaRBpBow/5wgzKwH1oh3Vqz+EIiSvGYksMJNa rYIg4VgOijS1WN7oNI8MSQ8FY1f8PAV9tu6T2tyBGoPxUVQ80KINHDlohpKd4Fp5jUWi 4NhUXKI9m8Wg07TzfFgNMB0x4ZI84EQt8sYjW98CV01uddacWuy4iBcu15MYDn3bCpGe KP4j507AAmzlxeQKMewfiB2Se/92HEFizTGjT0Efje0IYeG37CpLdUSeWdlIX2Ee9ZLF s61Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b/FueGBlYNAFQ/RajAwMkRjKV4N3VX+Jcw4nXuRvfOs=; b=PMTjMUdjr/nmqiBAWOHGd/MzECOfmXP60YqbQogooOCugubRf4VLu6oPTDX6K1/DVT PGTTJv9dAv/4qetJKLsqJ1DUQkzAN5QAFVZKVR9TQYllVHF4v2/xvFg5xDoLIDAFgNUC +wpvGkjHFyS5/uCAtOlnF2pAZPLe2ibwUiVMOXiAq8jPX6gmmNMc24Kp4bfUngiAGLDq 3zQkST7nVeqG4ChVwieUz7cPFb67Vnp1pw6yj9Ch1Bdw62qZ44dZ/I4lflOq6eiR6zi5 wyZzz4fGvv3aLDizbyTioz99ULYaeK5M9x4PX0DPDpK+a6A9SV5pdzs9Vf3B8unUIllf gcYA== X-Gm-Message-State: AHYfb5jC31HV4fWppv7eJKbNoxKVZSNQVpUed9U2K7gIyE6qx3McrgIU vder1uH904F0D7h5C1U= X-Received: by 10.46.21.84 with SMTP id 20mr2237823ljv.72.1501965008065; Sat, 05 Aug 2017 13:30:08 -0700 (PDT) From: Aleksandr Bezzubikov To: seabios@seabios.org Date: Sat, 5 Aug 2017 23:29:54 +0300 Message-Id: <1501964994-5257-4-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501964994-5257-1-git-send-email-zuban32s@gmail.com> References: <1501964994-5257-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -4.5 (----) Subject: [SeaBIOS] [PATCH v4 3/3] pci: enable RedHat PCI bridges to reserve additional buses on PCI init X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com, marcel@redhat.com, lersek@redhat.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" In case of Red Hat Generic PCIE Root Port reserve additional buses, which number is provided in a vendor-specific capability. Signed-off-by: Aleksandr Bezzubikov --- src/fw/pciinit.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++++= ---- src/hw/pci_ids.h | 3 +++ 2 files changed, 68 insertions(+), 4 deletions(-) diff --git a/src/fw/pciinit.c b/src/fw/pciinit.c index 864954f..d241d66 100644 --- a/src/fw/pciinit.c +++ b/src/fw/pciinit.c @@ -15,6 +15,7 @@ #include "hw/pcidevice.h" // pci_probe_devices #include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL #include "hw/pci_regs.h" // PCI_COMMAND +#include "fw/dev-pci.h" // qemu_pci_cap #include "list.h" // struct hlist_node #include "malloc.h" // free #include "output.h" // dprintf @@ -578,9 +579,42 @@ pci_bios_init_bus_rec(int bus, u8 *pci_bus) pci_bios_init_bus_rec(secbus, pci_bus); =20 if (subbus !=3D *pci_bus) { + u8 res_bus =3D 0; + if (pci_config_readw(bdf, PCI_VENDOR_ID) =3D=3D PCI_VENDOR_ID_= REDHAT && + pci_config_readw(bdf, PCI_DEVICE_ID) =3D=3D + PCI_DEVICE_ID_REDHAT_ROOT_PORT) { + u8 cap; + do { + cap =3D pci_find_capability(bdf, PCI_CAP_ID_VNDR, 0); + } while (cap && + pci_config_readb(bdf, cap + PCI_CAP_REDHAT_TYPE) = !=3D + REDHAT_CAP_TYPE_QEMU); + if (cap) { + u8 cap_len =3D pci_config_readb(bdf, cap + PCI_CAP_FLA= GS); + if (cap_len !=3D QEMU_PCI_CAP_SIZE) { + dprintf(1, "PCI: QEMU cap length %d is invalid\n", + cap_len); + } else { + u32 tmp_res_bus =3D pci_config_readl(bdf, + cap + QEMU_PCI_CAP_BUS_= RES); + if (tmp_res_bus !=3D (u32)-1) { + res_bus =3D tmp_res_bus & 0xFF; + if ((u8)(res_bus + secbus) < secbus || + (u8)(res_bus + secbus) < res_bus) { + dprintf(1, "PCI: bus_reserve value %d is i= nvalid\n", + res_bus); + res_bus =3D 0; + } + } + } + } + res_bus =3D (*pci_bus > secbus + res_bus) ? *pci_bus + : secbus + res_bus; + } dprintf(1, "PCI: subordinate bus =3D 0x%x -> 0x%x\n", - subbus, *pci_bus); - subbus =3D *pci_bus; + subbus, res_bus); + subbus =3D res_bus; + *pci_bus =3D res_bus; } else { dprintf(1, "PCI: subordinate bus =3D 0x%x\n", subbus); } @@ -951,11 +985,38 @@ pci_region_map_one_entry(struct pci_region_entry *ent= ry, u64 addr) =20 u16 bdf =3D entry->dev->bdf; u64 limit =3D addr + entry->size - 1; + + if (pci_config_readw(bdf, PCI_VENDOR_ID) =3D=3D PCI_VENDOR_ID_REDHAT && + pci_config_readw(bdf, PCI_DEVICE_ID) =3D=3D + PCI_DEVICE_ID_REDHAT_ROOT_PORT) { + u8 cap; + do { + cap =3D pci_find_capability(bdf, PCI_CAP_ID_VNDR, 0); + } while (cap && + pci_config_readb(bdf, cap + PCI_CAP_REDHAT_TYPE) !=3D + REDHAT_CAP_TYPE_QEMU); + if (cap) { + u8 cap_len =3D pci_config_readb(bdf, cap + PCI_CAP_FLAGS); + if (cap_len !=3D QEMU_PCI_CAP_SIZE) { + dprintf(1, "PCI: QEMU cap length %d is invalid\n", + cap_len); + } else { + u32 offset =3D cap + QEMU_PCI_CAP_LIMITS_OFFSET + entry->t= ype * 8; + u64 tmp_limit =3D (pci_config_readl(bdf, offset) | + (u64)pci_config_readl(bdf, offset + 4) << 32); + if (tmp_limit !=3D (u64)-1) { + tmp_limit +=3D addr - 1; + limit =3D (limit > tmp_limit) ? limit : tmp_limit; + } + } + } + } + if (entry->type =3D=3D PCI_REGION_TYPE_IO) { pci_config_writeb(bdf, PCI_IO_BASE, addr >> PCI_IO_SHIFT); - pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0); + pci_config_writew(bdf, PCI_IO_BASE_UPPER16, limit >> 16); pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT); - pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0); + pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, limit >> 16); } if (entry->type =3D=3D PCI_REGION_TYPE_MEM) { pci_config_writew(bdf, PCI_MEMORY_BASE, addr >> PCI_MEMORY_SHIFT); diff --git a/src/hw/pci_ids.h b/src/hw/pci_ids.h index 4ac73b4..38fa2ca 100644 --- a/src/hw/pci_ids.h +++ b/src/hw/pci_ids.h @@ -2263,6 +2263,9 @@ #define PCI_DEVICE_ID_KORENIX_JETCARDF0 0x1600 #define PCI_DEVICE_ID_KORENIX_JETCARDF1 0x16ff =20 +#define PCI_VENDOR_ID_REDHAT 0x1b36 +#define PCI_DEVICE_ID_REDHAT_ROOT_PORT 0x000C + #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 =20 --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios