From nobody Thu May 2 14:22:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150186811408137.26546865519367; Fri, 4 Aug 2017 10:35:14 -0700 (PDT) Received: from localhost ([::1]:40636 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgVE-0000cH-Ho for importer@patchew.org; Fri, 04 Aug 2017 13:35:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47033) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgTH-0007VY-8h for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:33:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgTG-0001la-A7 for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:33:11 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37805) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgTE-0001gy-17; Fri, 04 Aug 2017 13:33:08 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHK-0006sG-Pd; Fri, 04 Aug 2017 18:20:50 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 4 Aug 2017 18:20:42 +0100 Message-Id: <1501867249-1924-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 1/8] memory.h: Move MemTxResult type to memattrs.h X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Move the MemTxResult type to memattrs.h. We're going to want to use it in cpu/qom.h, which doesn't want to include all of memory.h. In practice MemTxResult and MemTxAttrs are pretty closely linked since both are used for the new-style read_with_attrs and write_with_attrs callbacks, so memattrs.h is a reasonable home for this rather than creating a whole new header file for it. Signed-off-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson --- include/exec/memattrs.h | 10 ++++++++++ include/exec/memory.h | 10 ---------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index e601061..d4a1642 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -46,4 +46,14 @@ typedef struct MemTxAttrs { */ #define MEMTXATTRS_UNSPECIFIED ((MemTxAttrs) { .unspecified =3D 1 }) =20 +/* New-style MMIO accessors can indicate that the transaction failed. + * A zero (MEMTX_OK) response means success; anything else is a failure + * of some kind. The memory subsystem will bitwise-OR together results + * if it is synthesizing an operation from multiple smaller accesses. + */ +#define MEMTX_OK 0 +#define MEMTX_ERROR (1U << 0) /* device returned an error */ +#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */ +typedef uint32_t MemTxResult; + #endif diff --git a/include/exec/memory.h b/include/exec/memory.h index 400dd44..1dcd312 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -112,16 +112,6 @@ static inline void iommu_notifier_init(IOMMUNotifier *= n, IOMMUNotify fn, n->end =3D end; } =20 -/* New-style MMIO accessors can indicate that the transaction failed. - * A zero (MEMTX_OK) response means success; anything else is a failure - * of some kind. The memory subsystem will bitwise-OR together results - * if it is synthesizing an operation from multiple smaller accesses. - */ -#define MEMTX_OK 0 -#define MEMTX_ERROR (1U << 0) /* device returned an error */ -#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */ -typedef uint32_t MemTxResult; - /* * Memory region callbacks */ --=20 2.7.4 From nobody Thu May 2 14:22:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501868113457358.830309390529; Fri, 4 Aug 2017 10:35:13 -0700 (PDT) Received: from localhost ([::1]:40634 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgVD-0000Yv-G0 for importer@patchew.org; Fri, 04 Aug 2017 13:35:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46965) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgTF-0007Tj-2Y for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:33:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgTE-0001jN-1n for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:33:09 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37805) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgTB-0001gy-H3; Fri, 04 Aug 2017 13:33:05 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHL-0006sR-8c; Fri, 04 Aug 2017 18:20:51 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 4 Aug 2017 18:20:43 +0100 Message-Id: <1501867249-1924-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 2/8] cpu: Define new cpu_transaction_failed() hook X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently we have a rather half-baked setup for allowing CPUs to generate exceptions on accesses to invalid memory: the CPU has a cpu_unassigned_access() hook which the memory system calls in unassigned_mem_write() and unassigned_mem_read() if the current_cpu pointer is non-NULL. This was originally designed before we implemented the MemTxResult type that allows memory operations to report a success or failure code, which is why the hook is called right at the bottom of the memory system. The major problem with this is that it means that the hook can be called even when the access was not actually done by the CPU: for instance if the CPU writes to a DMA engine register which causes the DMA engine to begin a transaction which has been set up by the guest to operate on invalid memory then this will casue the CPU to take an exception incorrectly. Another minor problem is that currently if a device returns a transaction error then this won't turn into a CPU exception at all. The right way to do this is to have allow the CPU to respond to memory system transaction failures at the point where the CPU specific code calls into the memory system. Define a new QOM CPU method and utility function cpu_transaction_failed() which is called in these cases. The functionality here overlaps with the existing cpu_unassigned_access() because individual target CPUs will need some work to convert them to the new system. When this transition is complete we can remove the old cpu_unassigned_access() code. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson --- include/qom/cpu.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 25eefea..fc54d55 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -85,8 +85,10 @@ struct TranslationBlock; * @has_work: Callback for checking if there is work to do. * @do_interrupt: Callback for interrupt handling. * @do_unassigned_access: Callback for unassigned access handling. + * (this is deprecated: new targets should use do_transaction_failed inste= ad) * @do_unaligned_access: Callback for unaligned access handling, if * the target defines #ALIGNED_ONLY. + * @do_transaction_failed: Callback for handling failed memory transactions * @virtio_is_big_endian: Callback to return %true if a CPU which supports * runtime configurable endianness is currently big-endian. Non-configurab= le * CPUs can use the default implementation of this method. This method sho= uld @@ -153,6 +155,10 @@ typedef struct CPUClass { void (*do_unaligned_access)(CPUState *cpu, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); + void (*do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr ad= dr, + unsigned size, MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); bool (*virtio_is_big_endian)(CPUState *cpu); int (*memory_rw_debug)(CPUState *cpu, vaddr addr, uint8_t *buf, int len, bool is_write); @@ -837,6 +843,21 @@ static inline void cpu_unaligned_access(CPUState *cpu,= vaddr addr, =20 cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); } + +static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, + uintptr_t retaddr) +{ + CPUClass *cc =3D CPU_GET_CLASS(cpu); + + if (cc->do_transaction_failed) { + cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, + mmu_idx, attrs, response, retaddr); + } +} #endif =20 #endif /* NEED_CPU_H */ --=20 2.7.4 From nobody Thu May 2 14:22:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501868328094768.068946264173; Fri, 4 Aug 2017 10:38:48 -0700 (PDT) Received: from localhost ([::1]:40946 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgYg-0003h7-R3 for importer@patchew.org; Fri, 04 Aug 2017 13:38:46 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47040) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgTH-0007Vm-IA for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:33:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgTG-0001lj-DW for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:33:11 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37805) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgTD-0001gy-6T; Fri, 04 Aug 2017 13:33:07 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHL-0006si-N7; Fri, 04 Aug 2017 18:20:51 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 4 Aug 2017 18:20:44 +0100 Message-Id: <1501867249-1924-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 3/8] cputlb: Support generating CPU exceptions on memory transaction failures X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Call the new cpu_transaction_failed() hook at the places where CPU generated code interacts with the memory system: io_readx() io_writex() get_page_addr_code() Any access from C code (eg via cpu_physical_memory_rw(), address_space_rw(), ld/st_*_phys()) will *not* trigger CPU exceptions via cpu_transaction_failed(). Handling for transactions failures for this kind of call should be done by using a function which returns a MemTxResult and treating the failure case appropriately in the calling code. In an ideal world we would not generate CPU exceptions for instruction fetch failures in get_page_addr_code() but instead wait until the code translation process tried a load and it failed; however that change would require too great a restructuring and redesign to attempt at this point. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- softmmu_template.h | 4 ++-- accel/tcg/cputlb.c | 32 ++++++++++++++++++++++++++++++-- 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/softmmu_template.h b/softmmu_template.h index 4a2b665..d756329 100644 --- a/softmmu_template.h +++ b/softmmu_template.h @@ -101,7 +101,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchSt= ate *env, uintptr_t retaddr) { CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; - return io_readx(env, iotlbentry, addr, retaddr, DATA_SIZE); + return io_readx(env, iotlbentry, mmu_idx, addr, retaddr, DATA_SIZE); } #endif =20 @@ -262,7 +262,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState = *env, uintptr_t retaddr) { CPUIOTLBEntry *iotlbentry =3D &env->iotlb[mmu_idx][index]; - return io_writex(env, iotlbentry, val, addr, retaddr, DATA_SIZE); + return io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr, DATA_SI= ZE); } =20 void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 85635ae..e72415a 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -747,6 +747,7 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail= (void *ptr) } =20 static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry, + int mmu_idx, target_ulong addr, uintptr_t retaddr, int size) { CPUState *cpu =3D ENV_GET_CPU(env); @@ -754,6 +755,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, MemoryRegion *mr =3D iotlb_to_region(cpu, physaddr, iotlbentry->attrs); uint64_t val; bool locked =3D false; + MemTxResult r; =20 physaddr =3D (physaddr & TARGET_PAGE_MASK) + addr; cpu->mem_io_pc =3D retaddr; @@ -767,7 +769,12 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEn= try *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - memory_region_dispatch_read(mr, physaddr, &val, size, iotlbentry->attr= s); + r =3D memory_region_dispatch_read(mr, physaddr, + &val, size, iotlbentry->attrs); + if (r !=3D MEMTX_OK) { + cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_LOAD, + mmu_idx, iotlbentry->attrs, r, retaddr); + } if (locked) { qemu_mutex_unlock_iothread(); } @@ -776,6 +783,7 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEnt= ry *iotlbentry, } =20 static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry, + int mmu_idx, uint64_t val, target_ulong addr, uintptr_t retaddr, int size) { @@ -783,6 +791,7 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry = *iotlbentry, hwaddr physaddr =3D iotlbentry->addr; MemoryRegion *mr =3D iotlb_to_region(cpu, physaddr, iotlbentry->attrs); bool locked =3D false; + MemTxResult r; =20 physaddr =3D (physaddr & TARGET_PAGE_MASK) + addr; if (mr !=3D &io_mem_rom && mr !=3D &io_mem_notdirty && !cpu->can_do_io= ) { @@ -795,7 +804,12 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry= *iotlbentry, qemu_mutex_lock_iothread(); locked =3D true; } - memory_region_dispatch_write(mr, physaddr, val, size, iotlbentry->attr= s); + r =3D memory_region_dispatch_write(mr, physaddr, + val, size, iotlbentry->attrs); + if (r !=3D MEMTX_OK) { + cpu_transaction_failed(cpu, physaddr, addr, size, MMU_DATA_STORE, + mmu_idx, iotlbentry->attrs, r, retaddr); + } if (locked) { qemu_mutex_unlock_iothread(); } @@ -845,6 +859,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, ta= rget_ulong addr) MemoryRegion *mr; CPUState *cpu =3D ENV_GET_CPU(env); CPUIOTLBEntry *iotlbentry; + hwaddr physaddr; =20 index =3D (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); mmu_idx =3D cpu_mmu_index(env, true); @@ -868,6 +883,19 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env, t= arget_ulong addr) } qemu_mutex_unlock_iothread(); =20 + /* Give the new-style cpu_transaction_failed() hook first chance + * to handle this. + * This is not the ideal place to detect and generate CPU + * exceptions for instruction fetch failure (for instance + * we don't know the length of the access that the CPU would + * use, and it would be better to go ahead and try the access + * and use the MemTXResult it produced). However it is the + * simplest place we have currently available for the check. + */ + physaddr =3D (iotlbentry->addr & TARGET_PAGE_MASK) + addr; + cpu_transaction_failed(cpu, physaddr, addr, 0, MMU_INST_FETCH, mmu= _idx, + iotlbentry->attrs, MEMTX_DECODE_ERROR, 0); + cpu_unassigned_access(cpu, addr, false, true, 0, 4); /* The CPU's unassigned access hook might have longjumped out * with an exception. If it didn't (or there was no hook) then --=20 2.7.4 From nobody Thu May 2 14:22:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501868243722199.32698938086162; Fri, 4 Aug 2017 10:37:23 -0700 (PDT) Received: from localhost ([::1]:40825 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgXK-0002n5-Dv for importer@patchew.org; Fri, 04 Aug 2017 13:37:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47006) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgTG-0007Un-AQ for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:33:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgTF-0001kd-7h for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:33:10 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37805) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgTC-0001gy-Bg; Fri, 04 Aug 2017 13:33:06 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHM-0006sy-69; Fri, 04 Aug 2017 18:20:52 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 4 Aug 2017 18:20:45 +0100 Message-Id: <1501867249-1924-5-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 4/8] boards.h: Define new flag ignore_memory_transaction_failures X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Define a new MachineClass field ignore_memory_transaction_failures. If this is flag is true then the CPU will ignore memory transaction failures which should cause the CPU to take an exception due to an access to an unassigned physical address; the transaction will instead return zero (for a read) or be ignored (for a write). This should be set only by legacy board models which rely on the old RAZ/WI behaviour for handling devices that QEMU does not yet model. New board models should instead use "unimplemented-device" for all memory ranges where the guest will attempt to probe for a device that QEMU doesn't implement and a stub device is required. We need this for ARM boards, where we're about to implement support for generating external aborts on memory transaction failures. Too many of our legacy board models rely on the RAZ/WI behaviour and we would break currently working guests when their "probe for device" code provoked an external abort rather than a RAZ. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- include/hw/boards.h | 11 +++++++++++ include/qom/cpu.h | 7 ++++++- qom/cpu.c | 7 +++++++ 3 files changed, 24 insertions(+), 1 deletion(-) diff --git a/include/hw/boards.h b/include/hw/boards.h index 3363dd1..7f044d1 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -131,6 +131,16 @@ typedef struct { * size than the target architecture's minimum. (Attempting to create * such a CPU will fail.) Note that changing this is a migration * compatibility break for the machine. + * @ignore_memory_transaction_failures: + * If this is flag is true then the CPU will ignore memory transaction + * failures which should cause the CPU to take an exception due to an + * access to an unassigned physical address; the transaction will inste= ad + * return zero (for a read) or be ignored (for a write). This should be + * set only by legacy board models which rely on the old RAZ/WI behavio= ur + * for handling devices that QEMU does not yet model. New board models + * should instead use "unimplemented-device" for all memory ranges where + * the guest will attempt to probe for a device that QEMU doesn't + * implement and a stub device is required. */ struct MachineClass { /*< private >*/ @@ -171,6 +181,7 @@ struct MachineClass { bool rom_file_has_mr; int minimum_page_bits; bool has_hotpluggable_cpus; + bool ignore_memory_transaction_failures; int numa_mem_align_shift; void (*numa_auto_assign_ram)(MachineClass *mc, NodeInfo *nodes, int nb_nodes, ram_addr_t size); diff --git a/include/qom/cpu.h b/include/qom/cpu.h index fc54d55..8cff86f 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -311,6 +311,9 @@ struct qemu_work_item; * @trace_dstate_delayed: Delayed changes to trace_dstate (includes all ch= anges * to @trace_dstate). * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). + * @ignore_memory_transaction_failures: Cached copy of the MachineState + * flag of the same name: allows the board to suppress calling of the + * CPU do_transaction_failed hook function. * * State of one CPU core or thread. */ @@ -397,6 +400,8 @@ struct CPUState { */ bool throttle_thread_scheduled; =20 + bool ignore_memory_transaction_failures; + /* Note that this is accessed at the start of every TB via a negative offset from AREG0. Leave this field at the end so as to make the (absolute value) offset as small as possible. This reduces code @@ -853,7 +858,7 @@ static inline void cpu_transaction_failed(CPUState *cpu= , hwaddr physaddr, { CPUClass *cc =3D CPU_GET_CLASS(cpu); =20 - if (cc->do_transaction_failed) { + if (!cpu->ignore_memory_transaction_failures && cc->do_transaction_fai= led) { cc->do_transaction_failed(cpu, physaddr, addr, size, access_type, mmu_idx, attrs, response, retaddr); } diff --git a/qom/cpu.c b/qom/cpu.c index 4f38db0..d8dcf64 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -29,6 +29,7 @@ #include "exec/cpu-common.h" #include "qemu/error-report.h" #include "sysemu/sysemu.h" +#include "hw/boards.h" #include "hw/qdev-properties.h" #include "trace-root.h" =20 @@ -360,6 +361,12 @@ static void cpu_common_parse_features(const char *type= name, char *features, static void cpu_common_realizefn(DeviceState *dev, Error **errp) { CPUState *cpu =3D CPU(dev); + Object *machine =3D qdev_get_machine(); + ObjectClass *oc =3D object_get_class(machine); + MachineClass *mc =3D MACHINE_CLASS(oc); + + cpu->ignore_memory_transaction_failures =3D + mc->ignore_memory_transaction_failures; =20 if (dev->hotplugged) { cpu_synchronize_post_init(cpu); --=20 2.7.4 From nobody Thu May 2 14:22:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501868113540673.4175210915387; Fri, 4 Aug 2017 10:35:13 -0700 (PDT) Received: from localhost ([::1]:40632 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgVD-0000YK-Rx for importer@patchew.org; Fri, 04 Aug 2017 13:35:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47090) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgTM-0007by-Cz for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:33:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgTK-0001o5-2P for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:33:16 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37806) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgTF-0001ju-1j; Fri, 04 Aug 2017 13:33:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHM-0006tD-M1; Fri, 04 Aug 2017 18:20:52 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 4 Aug 2017 18:20:46 +0100 Message-Id: <1501867249-1924-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 5/8] hw/arm: Set ignore_memory_transaction_failures for most ARM boards X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Set the MachineClass flag ignore_memory_transaction_failures for almost all ARM boards. This means they retain the legacy behaviour that accesses to unimplemented addresses will RAZ/WI rather than aborting, when a subsequent commit adds support for external aborts. The exceptions are: * virt -- we know that guests won't try to prod devices that we don't describe in the device tree or ACPI tables * mps2 -- this board was written to use unimplemented-device for all the ranges with devices we don't yet handle New boards should not set the flag, but instead be written like the mps2. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- hw/arm/aspeed.c | 3 +++ hw/arm/collie.c | 1 + hw/arm/cubieboard.c | 1 + hw/arm/digic_boards.c | 1 + hw/arm/exynos4_boards.c | 2 ++ hw/arm/gumstix.c | 2 ++ hw/arm/highbank.c | 2 ++ hw/arm/imx25_pdk.c | 1 + hw/arm/integratorcp.c | 1 + hw/arm/kzm.c | 1 + hw/arm/mainstone.c | 1 + hw/arm/musicpal.c | 1 + hw/arm/netduino2.c | 1 + hw/arm/nseries.c | 2 ++ hw/arm/omap_sx1.c | 2 ++ hw/arm/palm.c | 1 + hw/arm/raspi.c | 1 + hw/arm/realview.c | 4 ++++ hw/arm/sabrelite.c | 1 + hw/arm/spitz.c | 4 ++++ hw/arm/stellaris.c | 2 ++ hw/arm/tosa.c | 1 + hw/arm/versatilepb.c | 2 ++ hw/arm/vexpress.c | 1 + hw/arm/xilinx_zynq.c | 1 + hw/arm/xlnx-ep108.c | 2 ++ hw/arm/z2.c | 1 + 27 files changed, 43 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 0c5635f..ab895ad 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -270,6 +270,7 @@ static void palmetto_bmc_class_init(ObjectClass *oc, vo= id *data) mc->no_floppy =3D 1; mc->no_cdrom =3D 1; mc->no_parallel =3D 1; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo palmetto_bmc_type =3D { @@ -302,6 +303,7 @@ static void ast2500_evb_class_init(ObjectClass *oc, voi= d *data) mc->no_floppy =3D 1; mc->no_cdrom =3D 1; mc->no_parallel =3D 1; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo ast2500_evb_type =3D { @@ -326,6 +328,7 @@ static void romulus_bmc_class_init(ObjectClass *oc, voi= d *data) mc->no_floppy =3D 1; mc->no_cdrom =3D 1; mc->no_parallel =3D 1; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo romulus_bmc_type =3D { diff --git a/hw/arm/collie.c b/hw/arm/collie.c index 2e69531..8830192 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -64,6 +64,7 @@ static void collie_machine_init(MachineClass *mc) { mc->desc =3D "Sharp SL-5500 (Collie) PDA (SA-1110)"; mc->init =3D collie_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("collie", collie_machine_init) diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index b98e1c4..32f1edd 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -86,6 +86,7 @@ static void cubieboard_machine_init(MachineClass *mc) mc->init =3D cubieboard_init; mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("cubieboard", cubieboard_machine_init) diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 520c8e9..9f11dcd 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -155,6 +155,7 @@ static void canon_a1100_machine_init(MachineClass *mc) { mc->desc =3D "Canon PowerShot A1100 IS"; mc->init =3D &canon_a1100_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("canon-a1100", canon_a1100_machine_init) diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 7c03ed3..f1441ec 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -189,6 +189,7 @@ static void nuri_class_init(ObjectClass *oc, void *data) mc->desc =3D "Samsung NURI board (Exynos4210)"; mc->init =3D nuri_init; mc->max_cpus =3D EXYNOS4210_NCPUS; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo nuri_type =3D { @@ -204,6 +205,7 @@ static void smdkc210_class_init(ObjectClass *oc, void *= data) mc->desc =3D "Samsung SMDKC210 board (Exynos4210)"; mc->init =3D smdkc210_init; mc->max_cpus =3D EXYNOS4210_NCPUS; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo smdkc210_type =3D { diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c index d59d9ba..092ce36 100644 --- a/hw/arm/gumstix.c +++ b/hw/arm/gumstix.c @@ -128,6 +128,7 @@ static void connex_class_init(ObjectClass *oc, void *da= ta) =20 mc->desc =3D "Gumstix Connex (PXA255)"; mc->init =3D connex_init; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo connex_type =3D { @@ -142,6 +143,7 @@ static void verdex_class_init(ObjectClass *oc, void *da= ta) =20 mc->desc =3D "Gumstix Verdex (PXA270)"; mc->init =3D verdex_init; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo verdex_type =3D { diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 20e60f1..0d222fe 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -410,6 +410,7 @@ static void highbank_class_init(ObjectClass *oc, void *= data) mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; mc->max_cpus =3D 4; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo highbank_type =3D { @@ -427,6 +428,7 @@ static void midway_class_init(ObjectClass *oc, void *da= ta) mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; mc->max_cpus =3D 4; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo midway_type =3D { diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index 7d42c74..9f3ee14 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -148,6 +148,7 @@ static void imx25_pdk_machine_init(MachineClass *mc) { mc->desc =3D "ARM i.MX25 PDK board (ARM926)"; mc->init =3D imx25_pdk_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init) diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index d9530ed..d603af9 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -681,6 +681,7 @@ static void integratorcp_machine_init(MachineClass *mc) { mc->desc =3D "ARM Integrator/CP (ARM926EJ-S)"; mc->init =3D integratorcp_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("integratorcp", integratorcp_machine_init) diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index 3ed6577..f9c2228 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -142,6 +142,7 @@ static void kzm_machine_init(MachineClass *mc) { mc->desc =3D "ARM KZM Emulation Baseboard (ARM1136)"; mc->init =3D kzm_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("kzm", kzm_machine_init) diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c index fb268e6..637f52c 100644 --- a/hw/arm/mainstone.c +++ b/hw/arm/mainstone.c @@ -196,6 +196,7 @@ static void mainstone2_machine_init(MachineClass *mc) { mc->desc =3D "Mainstone II (PXA27x)"; mc->init =3D mainstone_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("mainstone", mainstone2_machine_init) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 7e8ab31..fcf6224 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -1718,6 +1718,7 @@ static void musicpal_machine_init(MachineClass *mc) { mc->desc =3D "Marvell 88w8618 / MusicPal (ARM926EJ-S)"; mc->init =3D musicpal_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("musicpal", musicpal_machine_init) diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c index 3cfe332..9d34d4c 100644 --- a/hw/arm/netduino2.c +++ b/hw/arm/netduino2.c @@ -45,6 +45,7 @@ static void netduino2_machine_init(MachineClass *mc) { mc->desc =3D "Netduino 2 Machine"; mc->init =3D netduino2_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("netduino2", netduino2_machine_init) diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c index 503a3b6..a32ac82 100644 --- a/hw/arm/nseries.c +++ b/hw/arm/nseries.c @@ -1425,6 +1425,7 @@ static void n800_class_init(ObjectClass *oc, void *da= ta) mc->desc =3D "Nokia N800 tablet aka. RX-34 (OMAP2420)"; mc->init =3D n800_init; mc->default_boot_order =3D ""; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo n800_type =3D { @@ -1440,6 +1441,7 @@ static void n810_class_init(ObjectClass *oc, void *da= ta) mc->desc =3D "Nokia N810 tablet aka. RX-44 (OMAP2420)"; mc->init =3D n810_init; mc->default_boot_order =3D ""; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo n810_type =3D { diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 9809106..4535617 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -223,6 +223,7 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, = void *data) =20 mc->desc =3D "Siemens SX1 (OMAP310) V2"; mc->init =3D sx1_init_v2; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo sx1_machine_v2_type =3D { @@ -237,6 +238,7 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, = void *data) =20 mc->desc =3D "Siemens SX1 (OMAP310) V1"; mc->init =3D sx1_init_v1; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo sx1_machine_v1_type =3D { diff --git a/hw/arm/palm.c b/hw/arm/palm.c index 64cf8ca..bf070a2 100644 --- a/hw/arm/palm.c +++ b/hw/arm/palm.c @@ -274,6 +274,7 @@ static void palmte_machine_init(MachineClass *mc) { mc->desc =3D "Palm Tungsten|E aka. Cheetah PDA (OMAP310)"; mc->init =3D palmte_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("cheetah", palmte_machine_init) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 32cdc98..5941c9f 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -168,5 +168,6 @@ static void raspi2_machine_init(MachineClass *mc) mc->no_cdrom =3D 1; mc->max_cpus =3D BCM2836_NCPUS; mc->default_ram_size =3D 1024 * 1024 * 1024; + mc->ignore_memory_transaction_failures =3D true; }; DEFINE_MACHINE("raspi2", raspi2_machine_init) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 76ff557..f1b261f 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -396,6 +396,7 @@ static void realview_eb_class_init(ObjectClass *oc, voi= d *data) mc->desc =3D "ARM RealView Emulation Baseboard (ARM926EJ-S)"; mc->init =3D realview_eb_init; mc->block_default_type =3D IF_SCSI; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo realview_eb_type =3D { @@ -412,6 +413,7 @@ static void realview_eb_mpcore_class_init(ObjectClass *= oc, void *data) mc->init =3D realview_eb_mpcore_init; mc->block_default_type =3D IF_SCSI; mc->max_cpus =3D 4; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo realview_eb_mpcore_type =3D { @@ -426,6 +428,7 @@ static void realview_pb_a8_class_init(ObjectClass *oc, = void *data) =20 mc->desc =3D "ARM RealView Platform Baseboard for Cortex-A8"; mc->init =3D realview_pb_a8_init; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo realview_pb_a8_type =3D { @@ -441,6 +444,7 @@ static void realview_pbx_a9_class_init(ObjectClass *oc,= void *data) mc->desc =3D "ARM RealView Platform Baseboard Explore for Cortex-A9"; mc->init =3D realview_pbx_a9_init; mc->max_cpus =3D 4; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo realview_pbx_a9_type =3D { diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 4e7ac8c..ee140e5 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -122,6 +122,7 @@ static void sabrelite_machine_init(MachineClass *mc) mc->desc =3D "Freescale i.MX6 Quad SABRE Lite Board (Cortex A9)"; mc->init =3D sabrelite_init; mc->max_cpus =3D FSL_IMX6_NUM_CPUS; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("sabrelite", sabrelite_machine_init) diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 7f588ce..6406421 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -983,6 +983,7 @@ static void akitapda_class_init(ObjectClass *oc, void *= data) =20 mc->desc =3D "Sharp SL-C1000 (Akita) PDA (PXA270)"; mc->init =3D akita_init; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo akitapda_type =3D { @@ -998,6 +999,7 @@ static void spitzpda_class_init(ObjectClass *oc, void *= data) mc->desc =3D "Sharp SL-C3000 (Spitz) PDA (PXA270)"; mc->init =3D spitz_init; mc->block_default_type =3D IF_IDE; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo spitzpda_type =3D { @@ -1013,6 +1015,7 @@ static void borzoipda_class_init(ObjectClass *oc, voi= d *data) mc->desc =3D "Sharp SL-C3100 (Borzoi) PDA (PXA270)"; mc->init =3D borzoi_init; mc->block_default_type =3D IF_IDE; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo borzoipda_type =3D { @@ -1028,6 +1031,7 @@ static void terrierpda_class_init(ObjectClass *oc, vo= id *data) mc->desc =3D "Sharp SL-C3200 (Terrier) PDA (PXA270)"; mc->init =3D terrier_init; mc->block_default_type =3D IF_IDE; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo terrierpda_type =3D { diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 408c1a1..b3aad23 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1453,6 +1453,7 @@ static void lm3s811evb_class_init(ObjectClass *oc, vo= id *data) =20 mc->desc =3D "Stellaris LM3S811EVB"; mc->init =3D lm3s811evb_init; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo lm3s811evb_type =3D { @@ -1467,6 +1468,7 @@ static void lm3s6965evb_class_init(ObjectClass *oc, v= oid *data) =20 mc->desc =3D "Stellaris LM3S6965EVB"; mc->init =3D lm3s6965evb_init; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo lm3s6965evb_type =3D { diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c index 8b757ff..1134cf7 100644 --- a/hw/arm/tosa.c +++ b/hw/arm/tosa.c @@ -263,6 +263,7 @@ static void tosapda_machine_init(MachineClass *mc) mc->desc =3D "Sharp SL-6000 (Tosa) PDA (PXA255)"; mc->init =3D tosa_init; mc->block_default_type =3D IF_IDE; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("tosa", tosapda_machine_init) diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index b0e9f5b..76664e4 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -403,6 +403,7 @@ static void versatilepb_class_init(ObjectClass *oc, voi= d *data) mc->desc =3D "ARM Versatile/PB (ARM926EJ-S)"; mc->init =3D vpb_init; mc->block_default_type =3D IF_SCSI; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo versatilepb_type =3D { @@ -418,6 +419,7 @@ static void versatileab_class_init(ObjectClass *oc, voi= d *data) mc->desc =3D "ARM Versatile/AB (ARM926EJ-S)"; mc->init =3D vab_init; mc->block_default_type =3D IF_SCSI; + mc->ignore_memory_transaction_failures =3D true; } =20 static const TypeInfo versatileab_type =3D { diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 528c65d..9be1833 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -750,6 +750,7 @@ static void vexpress_class_init(ObjectClass *oc, void *= data) mc->desc =3D "ARM Versatile Express"; mc->init =3D vexpress_common_init; mc->max_cpus =3D 4; + mc->ignore_memory_transaction_failures =3D true; } =20 static void vexpress_a9_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 6b11a75..9883215 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -324,6 +324,7 @@ static void zynq_machine_init(MachineClass *mc) mc->init =3D zynq_init; mc->max_cpus =3D 1; mc->no_sdcard =3D 1; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) diff --git a/hw/arm/xlnx-ep108.c b/hw/arm/xlnx-ep108.c index 860780a..c339cd4 100644 --- a/hw/arm/xlnx-ep108.c +++ b/hw/arm/xlnx-ep108.c @@ -122,6 +122,7 @@ static void xlnx_ep108_machine_init(MachineClass *mc) mc->init =3D xlnx_ep108_init; mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("xlnx-ep108", xlnx_ep108_machine_init) @@ -132,6 +133,7 @@ static void xlnx_zcu102_machine_init(MachineClass *mc) mc->init =3D xlnx_ep108_init; mc->block_default_type =3D IF_IDE; mc->units_per_default_bus =3D 1; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("xlnx-zcu102", xlnx_zcu102_machine_init) diff --git a/hw/arm/z2.c b/hw/arm/z2.c index 1607cbd..417bc1a 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -370,6 +370,7 @@ static void z2_machine_init(MachineClass *mc) { mc->desc =3D "Zipit Z2 (PXA27x)"; mc->init =3D z2_init; + mc->ignore_memory_transaction_failures =3D true; } =20 DEFINE_MACHINE("z2", z2_machine_init) --=20 2.7.4 From nobody Thu May 2 14:22:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501867482342519.5427123509496; Fri, 4 Aug 2017 10:24:42 -0700 (PDT) Received: from localhost ([::1]:38908 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgL2-0001KL-Nk for importer@patchew.org; Fri, 04 Aug 2017 13:24:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39824) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgHa-0007JG-Qe for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:21:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgHZ-0001fJ-IA for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:21:06 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37794) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgHW-0001Dp-3J; Fri, 04 Aug 2017 13:21:02 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHN-0006to-DB; Fri, 04 Aug 2017 18:20:53 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 4 Aug 2017 18:20:47 +0100 Message-Id: <1501867249-1924-7-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 6/8] target/arm: Factor out fault delivery code X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We currently have some similar code in tlb_fill() and in arm_cpu_do_unaligned_access() for delivering a data abort or prefetch abort. We're also going to want to do the same thing to handle external aborts. Factor out the common code into a new function deliver_fault(). Signed-off-by: Peter Maydell Acked-by: Edgar E. Iglesias Reviewed-by: Richard Henderson --- target/arm/op_helper.c | 110 +++++++++++++++++++++++++--------------------= ---- 1 file changed, 57 insertions(+), 53 deletions(-) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 2a85666..aa52a98 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -115,6 +115,51 @@ static inline uint32_t merge_syn_data_abort(uint32_t t= emplate_syn, return syn; } =20 +static void deliver_fault(ARMCPU *cpu, vaddr addr, MMUAccessType access_ty= pe, + uint32_t fsr, uint32_t fsc, ARMMMUFaultInfo *fi) +{ + CPUARMState *env =3D &cpu->env; + int target_el; + bool same_el; + uint32_t syn, exc; + + target_el =3D exception_target_el(env); + if (fi->stage2) { + target_el =3D 2; + env->cp15.hpfar_el2 =3D extract64(fi->s2addr, 12, 47) << 4; + } + same_el =3D (arm_current_el(env) =3D=3D target_el); + + if (fsc =3D=3D 0x3f) { + /* Caller doesn't have a long-format fault status code. This + * should only happen if this fault will never actually be reported + * to an EL that uses a syndrome register. Check that here. + * 0x3f is a (currently) reserved FSR code, in case the constructed + * syndrome does leak into the guest somehow. + */ + assert(target_el !=3D 2 && !arm_el_is_aa64(env, target_el)); + } + + if (access_type =3D=3D MMU_INST_FETCH) { + syn =3D syn_insn_abort(same_el, 0, fi->s1ptw, fsc); + exc =3D EXCP_PREFETCH_ABORT; + } else { + syn =3D merge_syn_data_abort(env->exception.syndrome, target_el, + same_el, fi->s1ptw, + access_type =3D=3D MMU_DATA_STORE, + fsc); + if (access_type =3D=3D MMU_DATA_STORE + && arm_feature(env, ARM_FEATURE_V6)) { + fsr |=3D (1 << 11); + } + exc =3D EXCP_DATA_ABORT; + } + + env->exception.vaddress =3D addr; + env->exception.fsr =3D fsr; + raise_exception(env, exc, syn, target_el); +} + /* try to fill the TLB and return an exception if error. If retaddr is * NULL, it means that the function was called in C code (i.e. not * from generated code or from helper.c) @@ -129,23 +174,13 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAcc= essType access_type, ret =3D arm_tlb_fill(cs, addr, access_type, mmu_idx, &fsr, &fi); if (unlikely(ret)) { ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - uint32_t syn, exc, fsc; - unsigned int target_el; - bool same_el; + uint32_t fsc; =20 if (retaddr) { /* now we have a real cpu fault */ cpu_restore_state(cs, retaddr); } =20 - target_el =3D exception_target_el(env); - if (fi.stage2) { - target_el =3D 2; - env->cp15.hpfar_el2 =3D extract64(fi.s2addr, 12, 47) << 4; - } - same_el =3D arm_current_el(env) =3D=3D target_el; - if (fsr & (1 << 9)) { /* LPAE format fault status register : bottom 6 bits are * status code in the same form as needed for syndrome @@ -153,34 +188,15 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAcc= essType access_type, fsc =3D extract32(fsr, 0, 6); } else { /* Short format FSR : this fault will never actually be report= ed - * to an EL that uses a syndrome register. Check that here, - * and use a (currently) reserved FSR code in case the constru= cted - * syndrome does leak into the guest somehow. + * to an EL that uses a syndrome register. Use a (currently) + * reserved FSR code in case the constructed syndrome does leak + * into the guest somehow. deliver_fault will assert that + * we don't target an EL using the syndrome. */ - assert(target_el !=3D 2 && !arm_el_is_aa64(env, target_el)); fsc =3D 0x3f; } =20 - /* For insn and data aborts we assume there is no instruction synd= rome - * information; this is always true for exceptions reported to EL1. - */ - if (access_type =3D=3D MMU_INST_FETCH) { - syn =3D syn_insn_abort(same_el, 0, fi.s1ptw, fsc); - exc =3D EXCP_PREFETCH_ABORT; - } else { - syn =3D merge_syn_data_abort(env->exception.syndrome, target_e= l, - same_el, fi.s1ptw, - access_type =3D=3D MMU_DATA_STORE, = fsc); - if (access_type =3D=3D MMU_DATA_STORE - && arm_feature(env, ARM_FEATURE_V6)) { - fsr |=3D (1 << 11); - } - exc =3D EXCP_DATA_ABORT; - } - - env->exception.vaddress =3D addr; - env->exception.fsr =3D fsr; - raise_exception(env, exc, syn, target_el); + deliver_fault(cpu, addr, access_type, fsr, fsc, &fi); } } =20 @@ -191,9 +207,8 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr va= ddr, { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; - int target_el; - bool same_el; - uint32_t syn; + uint32_t fsr, fsc; + ARMMMUFaultInfo fi =3D {}; ARMMMUIdx arm_mmu_idx =3D core_to_arm_mmu_idx(env, mmu_idx); =20 if (retaddr) { @@ -201,28 +216,17 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr = vaddr, cpu_restore_state(cs, retaddr); } =20 - target_el =3D exception_target_el(env); - same_el =3D (arm_current_el(env) =3D=3D target_el); - - env->exception.vaddress =3D vaddr; - /* the DFSR for an alignment fault depends on whether we're using * the LPAE long descriptor format, or the short descriptor format */ if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { - env->exception.fsr =3D (1 << 9) | 0x21; + fsr =3D (1 << 9) | 0x21; } else { - env->exception.fsr =3D 0x1; - } - - if (access_type =3D=3D MMU_DATA_STORE && arm_feature(env, ARM_FEATURE_= V6)) { - env->exception.fsr |=3D (1 << 11); + fsr =3D 0x1; } + fsc =3D 0x21; =20 - syn =3D merge_syn_data_abort(env->exception.syndrome, target_el, - same_el, 0, access_type =3D=3D MMU_DATA_STO= RE, - 0x21); - raise_exception(env, EXCP_DATA_ABORT, syn, target_el); + deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi); } =20 #endif /* !defined(CONFIG_USER_ONLY) */ --=20 2.7.4 From nobody Thu May 2 14:22:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501867367031618.1954291229952; Fri, 4 Aug 2017 10:22:47 -0700 (PDT) Received: from localhost ([::1]:38658 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgJB-0008G3-Ex for importer@patchew.org; Fri, 04 Aug 2017 13:22:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39796) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgHY-0007Gq-Nf for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:21:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgHX-0001bF-PF for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:21:04 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37794) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgHV-0001Dp-7X; Fri, 04 Aug 2017 13:21:01 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHN-0006u2-V1; Fri, 04 Aug 2017 18:20:53 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 4 Aug 2017 18:20:48 +0100 Message-Id: <1501867249-1924-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 7/8] target/arm: Allow deliver_fault() caller to specify EA bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For external aborts, we will want to be able to specify the EA (external abort type) bit in the syndrome field. Allow callers of deliver_fault() to do that by adding a field to ARMMMUFaultInfo which we use when constructing the syndrome values. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson --- target/arm/internals.h | 2 ++ target/arm/op_helper.c | 10 +++++----- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1f6efef..a3adbd8 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -448,12 +448,14 @@ void arm_handle_psci_call(ARMCPU *cpu); * @s2addr: Address that caused a fault at stage 2 * @stage2: True if we faulted at stage 2 * @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table = walk + * @ea: True if we should set the EA (external abort type) bit in syndrome */ typedef struct ARMMMUFaultInfo ARMMMUFaultInfo; struct ARMMMUFaultInfo { target_ulong s2addr; bool stage2; bool s1ptw; + bool ea; }; =20 /* Do a page table walk and add page to TLB if possible */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index aa52a98..7eac272 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -80,7 +80,7 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg= , uint32_t def, =20 static inline uint32_t merge_syn_data_abort(uint32_t template_syn, unsigned int target_el, - bool same_el, + bool same_el, bool ea, bool s1ptw, bool is_write, int fsc) { @@ -99,7 +99,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t temp= late_syn, */ if (!(template_syn & ARM_EL_ISV) || target_el !=3D 2 || s1ptw) { syn =3D syn_data_abort_no_iss(same_el, - 0, 0, s1ptw, is_write, fsc); + ea, 0, s1ptw, is_write, fsc); } else { /* Fields: IL, ISV, SAS, SSE, SRT, SF and AR come from the template * syndrome created at translation time. @@ -107,7 +107,7 @@ static inline uint32_t merge_syn_data_abort(uint32_t te= mplate_syn, */ syn =3D syn_data_abort_with_iss(same_el, 0, 0, 0, 0, 0, - 0, 0, s1ptw, is_write, fsc, + ea, 0, s1ptw, is_write, fsc, false); /* Merge the runtime syndrome with the template syndrome. */ syn |=3D template_syn; @@ -141,11 +141,11 @@ static void deliver_fault(ARMCPU *cpu, vaddr addr, MM= UAccessType access_type, } =20 if (access_type =3D=3D MMU_INST_FETCH) { - syn =3D syn_insn_abort(same_el, 0, fi->s1ptw, fsc); + syn =3D syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); exc =3D EXCP_PREFETCH_ABORT; } else { syn =3D merge_syn_data_abort(env->exception.syndrome, target_el, - same_el, fi->s1ptw, + same_el, fi->ea, fi->s1ptw, access_type =3D=3D MMU_DATA_STORE, fsc); if (access_type =3D=3D MMU_DATA_STORE --=20 2.7.4 From nobody Thu May 2 14:22:14 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501867481513599.9009777158684; Fri, 4 Aug 2017 10:24:41 -0700 (PDT) Received: from localhost ([::1]:38906 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgL2-0001Jx-1Q for importer@patchew.org; Fri, 04 Aug 2017 13:24:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39799) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ddgHY-0007Gx-Qr for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:21:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ddgHX-0001ba-RW for qemu-devel@nongnu.org; Fri, 04 Aug 2017 13:21:04 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37794) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1ddgHU-0001Dp-CX; Fri, 04 Aug 2017 13:21:00 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1ddgHO-0006uU-DU; Fri, 04 Aug 2017 18:20:54 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 4 Aug 2017 18:20:49 +0100 Message-Id: <1501867249-1924-9-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> References: <1501867249-1924-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 8/8] target/arm: Implement new do_transaction_failed hook X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement the new do_transaction_failed hook for ARM, which should cause the CPU to take a prefetch abort or data abort. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson --- target/arm/internals.h | 10 ++++++++++ target/arm/cpu.c | 1 + target/arm/op_helper.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index a3adbd8..13bb001 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -471,6 +471,16 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr v= addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); =20 +/* arm_cpu_do_transaction_failed: handle a memory system error response + * (eg "no device/memory present at address") by raising an external abort + * exception + */ +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr= ); + /* Call the EL change hook if one has been registered */ static inline void arm_call_el_change_hook(ARMCPU *cpu) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 05c038b..6baede0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1670,6 +1670,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) #else cc->do_interrupt =3D arm_cpu_do_interrupt; cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; + cc->do_transaction_failed =3D arm_cpu_do_transaction_failed; cc->get_phys_page_attrs_debug =3D arm_cpu_get_phys_page_attrs_debug; cc->asidx_from_attrs =3D arm_asidx_from_attrs; cc->vmsd =3D &vmstate_arm_cpu; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 7eac272..54b6dd8 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -229,6 +229,49 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr v= addr, deliver_fault(cpu, vaddr, access_type, fsr, fsc, &fi); } =20 +/* arm_cpu_do_transaction_failed: handle a memory system error response + * (eg "no device/memory present at address") by raising an external abort + * exception + */ +void arm_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + uint32_t fsr, fsc; + ARMMMUFaultInfo fi =3D {}; + ARMMMUIdx arm_mmu_idx =3D core_to_arm_mmu_idx(env, mmu_idx); + + if (retaddr) { + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr); + } + + /* The EA bit in syndromes and fault status registers is an + * IMPDEF classification of external aborts. ARM implementations + * usually use this to indicate AXI bus Decode error (0) or + * Slave error (1); in QEMU we follow that. + */ + fi.ea =3D (response !=3D MEMTX_DECODE_ERROR); + + /* The fault status register format depends on whether we're using + * the LPAE long descriptor format, or the short descriptor format. + */ + if (arm_s1_regime_using_lpae_format(env, arm_mmu_idx)) { + /* long descriptor form, STATUS 0b010000: synchronous ext abort */ + fsr =3D (fi.ea << 12) | (1 << 9) | 0x10; + } else { + /* short descriptor form, FSR 0b01000 : synchronous ext abort */ + fsr =3D (fi.ea << 12) | 0x8; + } + fsc =3D 0x10; + + deliver_fault(cpu, addr, access_type, fsr, fsc, &fi); +} + #endif /* !defined(CONFIG_USER_ONLY) */ =20 uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) --=20 2.7.4