From nobody Mon Feb 9 22:04:19 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501692813532726.5817830953358; Wed, 2 Aug 2017 09:53:33 -0700 (PDT) Received: from localhost ([::1]:48719 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwto-0002Lo-5W for importer@patchew.org; Wed, 02 Aug 2017 12:53:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49675) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwlF-0003fJ-0H for qemu-devel@nongnu.org; Wed, 02 Aug 2017 12:44:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwlE-0004sf-0X for qemu-devel@nongnu.org; Wed, 02 Aug 2017 12:44:41 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwlB-0003zA-Ka; Wed, 02 Aug 2017 12:44:37 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkd-0003wq-SX; Wed, 02 Aug 2017 17:44:03 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Wed, 2 Aug 2017 17:43:49 +0100 Message-Id: <1501692241-23310-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 03/15] target/arm: Consolidate PMSA handling in get_phys_addr() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently get_phys_addr() has PMSAv7 handling before the "is translation disabled?" check, and then PMSAv5 after it. Tidy this up by making the PMSAv5 code handle the "MPU disabled" case itself, so that we have all the PMSA code in one place. This will make adding the PMSAv8 code slightly cleaner, and also means that pre-v7 PMSA cores benefit from the MPU lookup logging that the PMSAv7 codepath had. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b78d277..fd83a21 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8423,6 +8423,13 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, u= int32_t address, uint32_t base; bool is_user =3D regime_is_user(env, mmu_idx); =20 + if (regime_translation_disabled(env, mmu_idx)) { + /* MPU disabled. */ + *phys_ptr =3D address; + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return false; + } + *phys_ptr =3D address; for (n =3D 7; n >=3D 0; n--) { base =3D env->cp15.c6_region[n]; @@ -8572,16 +8579,20 @@ static bool get_phys_addr(CPUARMState *env, target_= ulong address, } } =20 - /* pmsav7 has special handling for when MPU is disabled so call it bef= ore - * the common MMU/MPU disabled check below. - */ - if (arm_feature(env, ARM_FEATURE_PMSA) && - arm_feature(env, ARM_FEATURE_V7)) { + if (arm_feature(env, ARM_FEATURE_PMSA)) { bool ret; *page_size =3D TARGET_PAGE_SIZE; - ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_idx, - phys_ptr, prot, fsr); - qemu_log_mask(CPU_LOG_MMU, "PMSAv7 MPU lookup for %s at 0x%08" PRI= x32 + + if (arm_feature(env, ARM_FEATURE_V7)) { + /* PMSAv7 */ + ret =3D get_phys_addr_pmsav7(env, address, access_type, mmu_id= x, + phys_ptr, prot, fsr); + } else { + /* Pre-v7 MPU */ + ret =3D get_phys_addr_pmsav5(env, address, access_type, mmu_id= x, + phys_ptr, prot, fsr); + } + qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32 " mmu_idx %u -> %s (prot %c%c%c)\n", access_type =3D=3D MMU_DATA_LOAD ? "reading" : (access_type =3D=3D MMU_DATA_STORE ? "writing" : "ex= ecute"), @@ -8594,21 +8605,16 @@ static bool get_phys_addr(CPUARMState *env, target_= ulong address, return ret; } =20 + /* Definitely a real MMU, not an MPU */ + if (regime_translation_disabled(env, mmu_idx)) { - /* MMU/MPU disabled. */ + /* MMU disabled. */ *phys_ptr =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; *page_size =3D TARGET_PAGE_SIZE; return 0; } =20 - if (arm_feature(env, ARM_FEATURE_PMSA)) { - /* Pre-v7 MPU */ - *page_size =3D TARGET_PAGE_SIZE; - return get_phys_addr_pmsav5(env, address, access_type, mmu_idx, - phys_ptr, prot, fsr); - } - if (regime_using_lpae_format(env, mmu_idx)) { return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys= _ptr, attrs, prot, page_size, fsr, fi); --=20 2.7.4