From nobody Mon Feb 9 17:24:20 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501692876431383.57549261199506; Wed, 2 Aug 2017 09:54:36 -0700 (PDT) Received: from localhost ([::1]:48723 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwun-0003Un-7Y for importer@patchew.org; Wed, 02 Aug 2017 12:54:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49489) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dcwl8-0003Y3-78 for qemu-devel@nongnu.org; Wed, 02 Aug 2017 12:44:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dcwl7-0004kC-CY for qemu-devel@nongnu.org; Wed, 02 Aug 2017 12:44:34 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37764) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dcwl4-0003zA-V0; Wed, 02 Aug 2017 12:44:31 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dcwkh-0003zm-U3; Wed, 02 Aug 2017 17:44:07 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Wed, 2 Aug 2017 17:43:57 +0100 Message-Id: <1501692241-23310-12-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> References: <1501692241-23310-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 11/15] target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Make the arm_cpu_dump_state() debug logging handle the M-profile XPSR rather than assuming it's an A-profile CPSR. On M profile the PSR line of a register dump will now look like this: XPSR=3D41000000 -Z-- T priv-thread Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias Reviewed-by: Richard Henderson --- target/arm/translate.c | 58 ++++++++++++++++++++++++++++++++++------------= ---- 1 file changed, 40 insertions(+), 18 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 3c14cb0..e52a6d7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12215,8 +12215,6 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fpri= ntf_function cpu_fprintf, ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; int i; - uint32_t psr; - const char *ns_status; =20 if (is_a64(env)) { aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags); @@ -12230,24 +12228,48 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fp= rintf_function cpu_fprintf, else cpu_fprintf(f, " "); } - psr =3D cpsr_read(env); =20 - if (arm_feature(env, ARM_FEATURE_EL3) && - (psr & CPSR_M) !=3D ARM_CPU_MODE_MON) { - ns_status =3D env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + if (arm_feature(env, ARM_FEATURE_M)) { + uint32_t xpsr =3D xpsr_read(env); + const char *mode; + + if (xpsr & XPSR_EXCP) { + mode =3D "handler"; + } else { + if (env->v7m.control & R_V7M_CONTROL_NPRIV_MASK) { + mode =3D "unpriv-thread"; + } else { + mode =3D "priv-thread"; + } + } + + cpu_fprintf(f, "XPSR=3D%08x %c%c%c%c %c %s\n", + xpsr, + xpsr & XPSR_N ? 'N' : '-', + xpsr & XPSR_Z ? 'Z' : '-', + xpsr & XPSR_C ? 'C' : '-', + xpsr & XPSR_V ? 'V' : '-', + xpsr & XPSR_T ? 'T' : 'A', + mode); } else { - ns_status =3D ""; - } - - cpu_fprintf(f, "PSR=3D%08x %c%c%c%c %c %s%s%d\n", - psr, - psr & (1 << 31) ? 'N' : '-', - psr & (1 << 30) ? 'Z' : '-', - psr & (1 << 29) ? 'C' : '-', - psr & (1 << 28) ? 'V' : '-', - psr & CPSR_T ? 'T' : 'A', - ns_status, - cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); + uint32_t psr =3D cpsr_read(env); + const char *ns_status =3D ""; + + if (arm_feature(env, ARM_FEATURE_EL3) && + (psr & CPSR_M) !=3D ARM_CPU_MODE_MON) { + ns_status =3D env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + } + + cpu_fprintf(f, "PSR=3D%08x %c%c%c%c %c %s%s%d\n", + psr, + psr & CPSR_N ? 'N' : '-', + psr & CPSR_Z ? 'Z' : '-', + psr & CPSR_C ? 'C' : '-', + psr & CPSR_V ? 'V' : '-', + psr & CPSR_T ? 'T' : 'A', + ns_status, + cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); + } =20 if (flags & CPU_DUMP_FPU) { int numvfpregs =3D 0; --=20 2.7.4