From nobody Wed Apr 9 16:04:11 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501504006064410.14164204130134; Mon, 31 Jul 2017 05:26:46 -0700 (PDT) Received: from localhost ([::1]:59309 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9mV-0004m0-6b for importer@patchew.org; Mon, 31 Jul 2017 08:26:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56021) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9is-0001e8-R0 for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dc9ir-0003iF-OV for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:58 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37752) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dc9ir-0003ax-Gd for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:22:57 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dc9ii-0000tc-BA for qemu-devel@nongnu.org; Mon, 31 Jul 2017 13:22:48 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 31 Jul 2017 13:22:43 +0100 Message-Id: <1501503765-15639-6-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> References: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 5/7] target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 When the PMSAv7 implementation was originally added it was for R profile CPUs only, and reset was handled using the cpreg .resetfn hooks. Unfortunately for M profile cores this doesn't work, because they do not register any cpregs. Move the reset handling into arm_cpu_reset(), where it will work for both R profile and M profile cores. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 1501153150-19984-5-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.c | 14 ++++++++++++++ target/arm/helper.c | 28 ++++++++++++---------------- 2 files changed, 26 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 96d1f84..05c038b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -232,6 +232,20 @@ static void arm_cpu_reset(CPUState *s) =20 env->vfp.xregs[ARM_VFP_FPEXC] =3D 0; #endif + + if (arm_feature(env, ARM_FEATURE_PMSA) && + arm_feature(env, ARM_FEATURE_V7)) { + if (cpu->pmsav7_dregion > 0) { + memset(env->pmsav7.drbar, 0, + sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion); + memset(env->pmsav7.drsr, 0, + sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion); + memset(env->pmsav7.dracr, 0, + sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion); + } + env->pmsav7.rnr =3D 0; + } + set_flush_to_zero(1, &env->vfp.standard_fp_status); set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status); set_default_nan_mode(1, &env->vfp.standard_fp_status); diff --git a/target/arm/helper.c b/target/arm/helper.c index 0f79b25..fa60040 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2404,18 +2404,6 @@ static void pmsav7_write(CPUARMState *env, const ARM= CPRegInfo *ri, *u32p =3D value; } =20 -static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri) -{ - ARMCPU *cpu =3D arm_env_get_cpu(env); - uint32_t *u32p =3D *(uint32_t **)raw_ptr(env, ri); - - if (!u32p) { - return; - } - - memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion); -} - static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2433,22 +2421,30 @@ static void pmsav7_rgnr_write(CPUARMState *env, con= st ARMCPRegInfo *ri, } =20 static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { + /* Reset for all these registers is handled in arm_cpu_reset(), + * because the PMSAv7 is also used by M-profile CPUs, which do + * not register cpregs but still need the state to be reset. + */ { .name =3D "DRBAR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, = .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, pmsav7.drbar), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .resetfn =3D pms= av7_reset }, + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, + .resetfn =3D arm_cp_reset_ignore }, { .name =3D "DRSR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, .= opc2 =3D 2, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, pmsav7.drsr), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .resetfn =3D pms= av7_reset }, + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, + .resetfn =3D arm_cp_reset_ignore }, { .name =3D "DRACR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 1, = .opc2 =3D 4, .access =3D PL1_RW, .type =3D ARM_CP_NO_RAW, .fieldoffset =3D offsetof(CPUARMState, pmsav7.dracr), - .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .resetfn =3D pms= av7_reset }, + .readfn =3D pmsav7_read, .writefn =3D pmsav7_write, + .resetfn =3D arm_cp_reset_ignore }, { .name =3D "RGNR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 2, .= opc2 =3D 0, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr), - .writefn =3D pmsav7_rgnr_write }, + .writefn =3D pmsav7_rgnr_write, + .resetfn =3D arm_cp_reset_ignore }, REGINFO_SENTINEL }; =20 --=20 2.7.4