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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Mon, 31 Jul 2017 13:22:42 +0100
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Subject: [Qemu-devel] [PULL 4/7] target/arm: Rename cp15.c6_rgnr to
pmsav7.rnr
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Almost all of the PMSAv7 state is in the pmsav7 substruct of
the ARM CPU state structure. The exception is the region
number register, which is in cp15.c6_rgnr. This exception
is a bit odd for M profile, which otherwise generally does
not store state in the cp15 substruct.
Rename cp15.c6_rgnr to pmsav7.rnr accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Message-id: 1501153150-19984-4-git-send-email-peter.maydell@linaro.org
---
target/arm/cpu.h | 3 +--
hw/intc/armv7m_nvic.c | 14 +++++++-------
target/arm/helper.c | 6 +++---
target/arm/machine.c | 2 +-
4 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 102c58a..b39d64a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -305,8 +305,6 @@ typedef struct CPUARMState {
uint64_t par_el[4];
};
=20
- uint32_t c6_rgnr;
-
uint32_t c9_insn; /* Cache lockdown registers. */
uint32_t c9_data;
uint64_t c9_pmcr; /* performance monitor control register */
@@ -519,6 +517,7 @@ typedef struct CPUARMState {
uint32_t *drbar;
uint32_t *drsr;
uint32_t *dracr;
+ uint32_t rnr;
} pmsav7;
=20
void *nvic;
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 26a4b2d..323e2d4 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -536,13 +536,13 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off=
set)
case 0xd94: /* MPU_CTRL */
return cpu->env.v7m.mpu_ctrl;
case 0xd98: /* MPU_RNR */
- return cpu->env.cp15.c6_rgnr;
+ return cpu->env.pmsav7.rnr;
case 0xd9c: /* MPU_RBAR */
case 0xda4: /* MPU_RBAR_A1 */
case 0xdac: /* MPU_RBAR_A2 */
case 0xdb4: /* MPU_RBAR_A3 */
{
- int region =3D cpu->env.cp15.c6_rgnr;
+ int region =3D cpu->env.pmsav7.rnr;
=20
if (region >=3D cpu->pmsav7_dregion) {
return 0;
@@ -554,7 +554,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse=
t)
case 0xdb0: /* MPU_RASR_A2 */
case 0xdb8: /* MPU_RASR_A3 */
{
- int region =3D cpu->env.cp15.c6_rgnr;
+ int region =3D cpu->env.pmsav7.rnr;
=20
if (region >=3D cpu->pmsav7_dregion) {
return 0;
@@ -681,7 +681,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, =
uint32_t value)
PRIu32 "/%" PRIu32 "\n",
value, cpu->pmsav7_dregion);
} else {
- cpu->env.cp15.c6_rgnr =3D value;
+ cpu->env.pmsav7.rnr =3D value;
}
break;
case 0xd9c: /* MPU_RBAR */
@@ -702,9 +702,9 @@ static void nvic_writel(NVICState *s, uint32_t offset, =
uint32_t value)
region, cpu->pmsav7_dregion);
return;
}
- cpu->env.cp15.c6_rgnr =3D region;
+ cpu->env.pmsav7.rnr =3D region;
} else {
- region =3D cpu->env.cp15.c6_rgnr;
+ region =3D cpu->env.pmsav7.rnr;
}
=20
if (region >=3D cpu->pmsav7_dregion) {
@@ -720,7 +720,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, =
uint32_t value)
case 0xdb0: /* MPU_RASR_A2 */
case 0xdb8: /* MPU_RASR_A3 */
{
- int region =3D cpu->env.cp15.c6_rgnr;
+ int region =3D cpu->env.pmsav7.rnr;
=20
if (region >=3D cpu->pmsav7_dregion) {
return;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f0299c5..0f79b25 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2385,7 +2385,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const A=
RMCPRegInfo *ri)
return 0;
}
=20
- u32p +=3D env->cp15.c6_rgnr;
+ u32p +=3D env->pmsav7.rnr;
return *u32p;
}
=20
@@ -2399,7 +2399,7 @@ static void pmsav7_write(CPUARMState *env, const ARMC=
PRegInfo *ri,
return;
}
=20
- u32p +=3D env->cp15.c6_rgnr;
+ u32p +=3D env->pmsav7.rnr;
tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
*u32p =3D value;
}
@@ -2447,7 +2447,7 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D {
.readfn =3D pmsav7_read, .writefn =3D pmsav7_write, .resetfn =3D pms=
av7_reset },
{ .name =3D "RGNR", .cp =3D 15, .crn =3D 6, .opc1 =3D 0, .crm =3D 2, .=
opc2 =3D 0,
.access =3D PL1_RW,
- .fieldoffset =3D offsetof(CPUARMState, cp15.c6_rgnr),
+ .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr),
.writefn =3D pmsav7_rgnr_write },
REGINFO_SENTINEL
};
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 1a40469..93c1a78 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -151,7 +151,7 @@ static bool pmsav7_rgnr_vmstate_validate(void *opaque, =
int version_id)
{
ARMCPU *cpu =3D opaque;
=20
- return cpu->env.cp15.c6_rgnr < cpu->pmsav7_dregion;
+ return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion;
}
=20
static const VMStateDescription vmstate_pmsav7 =3D {
--=20
2.7.4