From nobody Wed Apr 9 16:57:54 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1501504176813906.4282167154447; Mon, 31 Jul 2017 05:29:36 -0700 (PDT) Received: from localhost ([::1]:59317 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9pH-0006rG-JO for importer@patchew.org; Mon, 31 Jul 2017 08:29:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56061) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dc9iv-0001ge-6N for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:23:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dc9iu-0003kG-5h for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:23:01 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:37752) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dc9it-0003ax-VB for qemu-devel@nongnu.org; Mon, 31 Jul 2017 08:23:00 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dc9ig-0000sH-Ta for qemu-devel@nongnu.org; Mon, 31 Jul 2017 13:22:46 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Mon, 31 Jul 2017 13:22:40 +0100 Message-Id: <1501503765-15639-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> References: <1501503765-15639-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 2/7] target/arm: Don't do MPU lookups for addresses in M profile PPB region X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 The M profile PMSAv7 specification says that if the address being looked up is in the PPB region (0xe0000000 - 0xe00fffff) then we do not use the MPU regions but always use the default memory map. Implement this (we were previously behaving like an R profile PMSAv7, which does not special case this). Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 1501153150-19984-2-git-send-email-peter.maydell@linaro.org --- target/arm/helper.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9ed5096..3d60575 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8244,6 +8244,13 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, } } =20 +static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) +{ + /* True if address is in the M profile PPB region 0xe0000000 - 0xe00ff= fff */ + return arm_feature(env, ARM_FEATURE_M) && + extract32(address, 20, 12) =3D=3D 0xe00; +} + static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, int access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, uint32_t *fs= r) @@ -8255,7 +8262,15 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, u= int32_t address, *phys_ptr =3D address; *prot =3D 0; =20 - if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */ + if (regime_translation_disabled(env, mmu_idx) || + m_is_ppb_region(env, address)) { + /* MPU disabled or M profile PPB access: use default memory map. + * The other case which uses the default memory map in the + * v7M ARM ARM pseudocode is exception vector reads from the vector + * table. In QEMU those accesses are done in arm_v7m_load_vector(), + * which always does a direct read using address_space_ldl(), rath= er + * than going via this function, so we don't need to check that he= re. + */ get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); } else { /* MPU enabled */ for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { --=20 2.7.4