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[178.140.16.138]) by smtp.gmail.com with ESMTPSA id t10sm757832lja.47.2017.07.22.15.16.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 22 Jul 2017 15:16:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uJODcaUN2fghYTMSE/DiWYdzbEjrlez4PlO02Mw1RLU=; b=gLMDeLv6UEtRqsru6GnlLZF+JGy6WU2EjlHvPtd9gnLFnHDtGe+4kTWP6c4Msb8SAj SkBHOTrqY3+N2YGjU+omGk2ayDHzTR4rp82OXQgxVDyzDemfoETOgJFpdOb3duSAWYdj UXz7vjRIcWDTr7XHD7tQIjv1hq9x/+5bu6phicMLXJg/srVjQTepALXo2lkzU8xlTlrP RCkJNTv0C7DB1GI13wxrZDjkbVhoU01jZ2DOUQLoDE/MCIME+CK23rhP4RyLYilFwUhP ErbTAJqaNTvokhQUbuxnvUqg2tho/johJt+zqBrnCUxb4lUlbq/TYsNPYzdnEL9thrv4 IrLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uJODcaUN2fghYTMSE/DiWYdzbEjrlez4PlO02Mw1RLU=; b=Zkb3BcigMNC8/In5HOxucdVV1rM/njpnD9xD9CL83EDC4lrgIzVoYyM3AcBzJOSAJy wNB1JXBBkdKNMmNNyHqf5+nnw03lMY+va6P8iEv6vVX01Cb9VlMPTeMbpV93To/N0rOm pPx7BrHCiUEnz3PSX2JM5S0rSslLZB5DQRQsToIrgrPJsrar4IrC4kn02dG4MEUixe0h p13Md78m1aE0OFm3kJCmTrBtHHFUFxSz4nPjviSzmJ+KK4MVJDs1+rK9ROcbqOvcjXFE x2GXGN7c1OLXdUbsMcMetUcP0X3rHRWEbV3k1frd/hLNz/vJ0g2En5fnhocWKEHfi+6t OdnQ== X-Gm-Message-State: AIVw110u826jRGUDQy4Tcff3dfG2Lw/r/N9bpDrL2Y4nNns56p2GGLeg CzlUzW1WXHRtJQ== X-Received: by 10.25.210.3 with SMTP id j3mr2108228lfg.86.1500761764188; Sat, 22 Jul 2017 15:16:04 -0700 (PDT) From: Aleksandr Bezzubikov To: qemu-devel@nongnu.org Date: Sun, 23 Jul 2017 01:15:41 +0300 Message-Id: <1500761743-1669-5-git-send-email-zuban32s@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> References: <1500761743-1669-1-git-send-email-zuban32s@gmail.com> X-Spam-Score: -4.5 (----) Subject: [SeaBIOS] [RFC PATCH v2 4/6] hw/pci: introduce bridge-only vendor-specific capability to provide some hints to firmware X-BeenThere: seabios@seabios.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: SeaBIOS mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mst@redhat.com, seabios@seabios.org, kraxel@redhat.com, pbonzini@redhat.com, marcel@redhat.com, rth@twiddle.net MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: seabios-bounces@seabios.org Sender: "SeaBIOS" X-Duff: Orig. Duff, Duff Lite, Duff Dry, Duff Dark, Raspberry Duff, Lady Duff, Red Duff, Tartar Control Duff X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" On PCI init PCI bridges may need some extra info about bus number to reserve, IO, memory and prefetchable memory limits. QEMU can provide this with special vendor-specific PCI capability. Sizes of limits match ones from PCI Type 1 Configuration Space Header, number of buses to reserve occupies only 1 byte=20 since it is the size of Subordinate Bus Number register. Signed-off-by: Aleksandr Bezzubikov --- hw/pci/pci_bridge.c | 27 +++++++++++++++++++++++++++ include/hw/pci/pci_bridge.h | 18 ++++++++++++++++++ 2 files changed, 45 insertions(+) diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index 720119b..8ec6c2c 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -408,6 +408,33 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus= _name, br->bus_name =3D bus_name; } =20 + +int pci_bridge_help_cap_init(PCIDevice *dev, int cap_offset, + uint8_t bus_reserve, uint32_t io_limit, + uint16_t mem_limit, uint64_t pref_limit, + Error **errp) +{ + size_t cap_len =3D sizeof(PCIBridgeQemuCap); + PCIBridgeQemuCap cap; + + cap.len =3D cap_len; + cap.bus_res =3D bus_reserve; + cap.io_lim =3D io_limit & 0xFF; + cap.io_lim_upper =3D io_limit >> 8 & 0xFFFF; + cap.mem_lim =3D mem_limit; + cap.pref_lim =3D pref_limit & 0xFFFF; + cap.pref_lim_upper =3D pref_limit >> 16 & 0xFFFFFFFF; + + int offset =3D pci_add_capability(dev, PCI_CAP_ID_VNDR, + cap_offset, cap_len, errp); + if (offset < 0) { + return offset; + } + + memcpy(dev->config + offset + 2, (char *)&cap + 2, cap_len - 2); + return 0; +} + static const TypeInfo pci_bridge_type_info =3D { .name =3D TYPE_PCI_BRIDGE, .parent =3D TYPE_PCI_DEVICE, diff --git a/include/hw/pci/pci_bridge.h b/include/hw/pci/pci_bridge.h index ff7cbaa..c9f642c 100644 --- a/include/hw/pci/pci_bridge.h +++ b/include/hw/pci/pci_bridge.h @@ -67,4 +67,22 @@ void pci_bridge_map_irq(PCIBridge *br, const char* bus_n= ame, #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */ =20 +typedef struct PCIBridgeQemuCap { + uint8_t id; /* Standard PCI capability header field */ + uint8_t next; /* Standard PCI capability header field */ + uint8_t len; /* Standard PCI vendor-specific capability header fiel= d */ + uint8_t bus_res; + uint32_t pref_lim_upper; + uint16_t pref_lim; + uint16_t mem_lim; + uint16_t io_lim_upper; + uint8_t io_lim; + uint8_t padding; +} PCIBridgeQemuCap; + +int pci_bridge_help_cap_init(PCIDevice *dev, int cap_offset, + uint8_t bus_reserve, uint32_t io_limit, + uint16_t mem_limit, uint64_t pref_limit, + Error **errp); + #endif /* QEMU_PCI_BRIDGE_H */ --=20 2.7.4 _______________________________________________ SeaBIOS mailing list SeaBIOS@seabios.org https://mail.coreboot.org/mailman/listinfo/seabios