From nobody Tue Feb 10 13:01:43 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500604773435147.1385119567633; Thu, 20 Jul 2017 19:39:33 -0700 (PDT) Received: from localhost ([::1]:40697 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dYNqm-0005Cy-5n for importer@patchew.org; Thu, 20 Jul 2017 22:39:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40080) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dYNoo-0003uU-C6 for qemu-devel@nongnu.org; Thu, 20 Jul 2017 22:37:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dYNon-0007Wt-43 for qemu-devel@nongnu.org; Thu, 20 Jul 2017 22:37:30 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:37177) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dYNom-0007Wd-SQ for qemu-devel@nongnu.org; Thu, 20 Jul 2017 22:37:29 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id 68CBCBA9CB77F; Fri, 21 Jul 2017 03:37:25 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Fri, 21 Jul 2017 03:37:27 +0100 From: Yongbok Kim To: Date: Fri, 21 Jul 2017 03:37:08 +0100 Message-ID: <1500604635-15027-8-git-send-email-yongbok.kim@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500604635-15027-1-git-send-email-yongbok.kim@imgtec.com> References: <1500604635-15027-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 07/14] target/mips: Decode microMIPS EVA load & store instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , James Hogan , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: James Hogan Implement decoding of microMIPS EVA load and store instruction groups in the POOL31C pool. These use the same gen_ld(), gen_st(), gen_st_cond() helpers as the MIPS32 decoding, passing the equivalent MIPS32 opcodes as opc. Signed-off-by: James Hogan Cc: Yongbok Kim Cc: Aurelien Jarno Reviewed-by: Yongbok Kim Signed-off-by: Yongbok Kim --- target/mips/translate.c | 119 ++++++++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 115 insertions(+), 4 deletions(-) diff --git a/target/mips/translate.c b/target/mips/translate.c index 93fb8f3..9787919 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -12519,19 +12519,45 @@ enum { LWR =3D 0x1, SWR =3D 0x9, PREF =3D 0x2, - /* 0xa is reserved */ + ST_EVA =3D 0xa, LL =3D 0x3, SC =3D 0xb, LDL =3D 0x4, SDL =3D 0xc, LDR =3D 0x5, SDR =3D 0xd, - /* 0x6 is reserved */ + LD_EVA =3D 0x6, LWU =3D 0xe, LLD =3D 0x7, SCD =3D 0xf }; =20 +/* POOL32C LD-EVA encoding of minor opcode field (bits 11..9) */ + +enum { + LBUE =3D 0x0, + LHUE =3D 0x1, + LWLE =3D 0x2, + LWRE =3D 0x3, + LBE =3D 0x4, + LHE =3D 0x5, + LLE =3D 0x6, + LWE =3D 0x7, +}; + +/* POOL32C ST-EVA encoding of minor opcode field (bits 11..9) */ + +enum { + SWLE =3D 0x0, + SWRE =3D 0x1, + PREFE =3D 0x2, + CACHEE =3D 0x3, + SBE =3D 0x4, + SHE =3D 0x5, + SCE =3D 0x6, + SWE =3D 0x7, +}; + /* POOL32F encoding of minor opcode field (bits 5..0) */ =20 enum { @@ -13832,7 +13858,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) uint16_t insn; int rt, rs, rd, rr; int16_t imm; - uint32_t op, minor, mips32_op; + uint32_t op, minor, minor2, mips32_op; uint32_t cond, fmt, cc; =20 insn =3D cpu_lduw_code(env, ctx->pc + 2); @@ -14777,7 +14803,7 @@ static void decode_micromips32_opc(CPUMIPSState *en= v, DisasContext *ctx) gen_ld(ctx, mips32_op, rt, rs, offset); break; do_st_lr: - gen_st(ctx, mips32_op, rt, rs, SIMM(ctx->opcode, 0, 12)); + gen_st(ctx, mips32_op, rt, rs, offset); break; case SC: gen_st_cond(ctx, OPC_SC, rt, rs, offset); @@ -14789,6 +14815,91 @@ static void decode_micromips32_opc(CPUMIPSState *e= nv, DisasContext *ctx) gen_st_cond(ctx, OPC_SCD, rt, rs, offset); break; #endif + case LD_EVA: + if (!ctx->eva) { + MIPS_INVAL("pool32c ld-eva"); + generate_exception_end(ctx, EXCP_RI); + break; + } + check_cp0_enabled(ctx); + + minor2 =3D (ctx->opcode >> 9) & 0x7; + offset =3D sextract32(ctx->opcode, 0, 9); + switch (minor2) { + case LBUE: + mips32_op =3D OPC_LBUE; + goto do_ld_lr; + case LHUE: + mips32_op =3D OPC_LHUE; + goto do_ld_lr; + case LWLE: + check_insn_opc_removed(ctx, ISA_MIPS32R6); + mips32_op =3D OPC_LWLE; + goto do_ld_lr; + case LWRE: + check_insn_opc_removed(ctx, ISA_MIPS32R6); + mips32_op =3D OPC_LWRE; + goto do_ld_lr; + case LBE: + mips32_op =3D OPC_LBE; + goto do_ld_lr; + case LHE: + mips32_op =3D OPC_LHE; + goto do_ld_lr; + case LLE: + mips32_op =3D OPC_LLE; + goto do_ld_lr; + case LWE: + mips32_op =3D OPC_LWE; + goto do_ld_lr; + }; + break; + case ST_EVA: + if (!ctx->eva) { + MIPS_INVAL("pool32c st-eva"); + generate_exception_end(ctx, EXCP_RI); + break; + } + check_cp0_enabled(ctx); + + minor2 =3D (ctx->opcode >> 9) & 0x7; + offset =3D sextract32(ctx->opcode, 0, 9); + switch (minor2) { + case SWLE: + check_insn_opc_removed(ctx, ISA_MIPS32R6); + mips32_op =3D OPC_SWLE; + goto do_st_lr; + case SWRE: + check_insn_opc_removed(ctx, ISA_MIPS32R6); + mips32_op =3D OPC_SWRE; + goto do_st_lr; + case PREFE: + /* Treat as no-op */ + if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >=3D 24)) { + /* hint codes 24-31 are reserved and signal RI */ + generate_exception(ctx, EXCP_RI); + } + break; + case CACHEE: + /* Treat as no-op */ + if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { + gen_cache_operation(ctx, rt, rs, offset); + } + break; + case SBE: + mips32_op =3D OPC_SBE; + goto do_st_lr; + case SHE: + mips32_op =3D OPC_SHE; + goto do_st_lr; + case SCE: + gen_st_cond(ctx, OPC_SCE, rt, rs, offset); + break; + case SWE: + mips32_op =3D OPC_SWE; + goto do_st_lr; + }; + break; case PREF: /* Treat as no-op */ if ((ctx->insn_flags & ISA_MIPS32R6) && (rt >=3D 24)) { --=20 2.7.4