From nobody Tue Feb 10 13:01:39 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150060509806884.03903645767025; Thu, 20 Jul 2017 19:44:58 -0700 (PDT) Received: from localhost ([::1]:40720 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dYNw0-0001BB-Mg for importer@patchew.org; Thu, 20 Jul 2017 22:44:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40180) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dYNot-0003yP-9c for qemu-devel@nongnu.org; Thu, 20 Jul 2017 22:37:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dYNor-0007a3-GP for qemu-devel@nongnu.org; Thu, 20 Jul 2017 22:37:35 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:18293) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dYNor-0007Zn-7B for qemu-devel@nongnu.org; Thu, 20 Jul 2017 22:37:33 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id F0CAC2CA8C071; Fri, 21 Jul 2017 03:37:28 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Fri, 21 Jul 2017 03:37:30 +0100 From: Yongbok Kim To: Date: Fri, 21 Jul 2017 03:37:13 +0100 Message-ID: <1500604635-15027-13-git-send-email-yongbok.kim@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500604635-15027-1-git-send-email-yongbok.kim@imgtec.com> References: <1500604635-15027-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 12/14] target/mips: Implement segmentation control X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , James Hogan , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: James Hogan Implement the optional segmentation control feature in the virtual to physical address translation code. The fixed legacy segment and xkphys handling is replaced with a dynamic layout based on the segmentation control registers (which should be set up even when the feature is not exposed to the guest). Signed-off-by: James Hogan Cc: Yongbok Kim Cc: Aurelien Jarno Reviewed-by: Yongbok Kim [yongbok.kim@imgtec.com: cosmetic changes] Signed-off-by: Yongbok Kim --- target/mips/helper.c | 191 ++++++++++++++++++++++++++++++++++++++++-------= ---- 1 file changed, 152 insertions(+), 39 deletions(-) diff --git a/target/mips/helper.c b/target/mips/helper.c index 7805e5c..a2b79e8 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -107,15 +107,107 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *phys= ical, int *prot, return TLBRET_NOMATCH; } =20 +static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) +{ + /* + * Interpret access control mode and mmu_idx. + * AdE? TLB? + * AM K S U E K S U E + * UK 0 0 1 1 0 0 - - 0 + * MK 1 0 1 1 0 1 - - !eu + * MSK 2 0 0 1 0 1 1 - !eu + * MUSK 3 0 0 0 0 1 1 1 !eu + * MUSUK 4 0 0 0 0 0 1 1 0 + * USK 5 0 0 1 0 0 0 - 0 + * - 6 - - - - - - - - + * UUSK 7 0 0 0 0 0 0 0 0 + */ + int32_t adetlb_mask; + + switch (mmu_idx) { + case 3 /* ERL */: + /* If EU is set, always unmapped */ + if (eu) { + return 0; + } + /* fall through */ + case MIPS_HFLAG_KM: + /* Never AdE, TLB mapped if AM=3D{1,2,3} */ + adetlb_mask =3D 0x70000000; + goto check_tlb; + + case MIPS_HFLAG_SM: + /* AdE if AM=3D{0,1}, TLB mapped if AM=3D{2,3,4} */ + adetlb_mask =3D 0xc0380000; + goto check_ade; + + case MIPS_HFLAG_UM: + /* AdE if AM=3D{0,1,2,5}, TLB mapped if AM=3D{3,4} */ + adetlb_mask =3D 0xe4180000; + /* fall through */ + check_ade: + /* does this AM cause AdE in current execution mode */ + if ((adetlb_mask << am) < 0) { + return TLBRET_BADADDR; + } + adetlb_mask <<=3D 8; + /* fall through */ + check_tlb: + /* is this AM mapped in current execution mode */ + return ((adetlb_mask << am) < 0); + default: + assert(0); + return TLBRET_BADADDR; + }; +} + +static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + int rw, int access_type, int mmu_idx, + unsigned int am, bool eu, + target_ulong segmask, + hwaddr physical_base) +{ + int mapped =3D is_seg_am_mapped(am, eu, mmu_idx); + + if (mapped < 0) { + /* is_seg_am_mapped can report TLBRET_BADADDR */ + return mapped; + } else if (mapped) { + /* The segment is TLB mapped */ + return env->tlb->map_address(env, physical, prot, real_address, rw, + access_type); + } else { + /* The segment is unmapped */ + *physical =3D physical_base | (real_address & segmask); + *prot =3D PAGE_READ | PAGE_WRITE; + return TLBRET_MATCH; + } +} + +static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_addres= s, + int rw, int access_type, int mmu_id= x, + uint16_t segctl, target_ulong segma= sk) +{ + unsigned int am =3D (segctl & CP0SC_AM_MASK) >> CP0SC_AM; + bool eu =3D (segctl >> CP0SC_EU) & 1; + hwaddr pa =3D ((hwaddr)segctl & CP0SC_PA_MASK) << 20; + + return get_seg_physical_address(env, physical, prot, real_address, rw, + access_type, mmu_idx, am, eu, segmask, + pa & ~(hwaddr)segmask); +} + static int get_physical_address (CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong real_address, int rw, int access_type, int mmu_idx) { /* User mode can only access useg/xuseg */ +#if defined(TARGET_MIPS64) int user_mode =3D mmu_idx =3D=3D MIPS_HFLAG_UM; int supervisor_mode =3D mmu_idx =3D=3D MIPS_HFLAG_SM; int kernel_mode =3D !user_mode && !supervisor_mode; -#if defined(TARGET_MIPS64) int UX =3D (env->CP0_Status & (1 << CP0St_UX)) !=3D 0; int SX =3D (env->CP0_Status & (1 << CP0St_SX)) !=3D 0; int KX =3D (env->CP0_Status & (1 << CP0St_KX)) !=3D 0; @@ -148,12 +240,16 @@ static int get_physical_address (CPUMIPSState *env, h= waddr *physical, =20 if (address <=3D USEG_LIMIT) { /* useg */ - if (env->CP0_Status & (1 << CP0St_ERL)) { - *physical =3D address & 0xFFFFFFFF; - *prot =3D PAGE_READ | PAGE_WRITE; + uint16_t segctl; + + if (address >=3D 0x40000000UL) { + segctl =3D env->CP0_SegCtl2; } else { - ret =3D env->tlb->map_address(env, physical, prot, real_addres= s, rw, access_type); + segctl =3D env->CP0_SegCtl2 >> 16; } + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, rw, + access_type, mmu_idx, segctl, + 0x3FFFFFFF); #if defined(TARGET_MIPS64) } else if (address < 0x4000000000000000ULL) { /* xuseg */ @@ -172,10 +268,33 @@ static int get_physical_address (CPUMIPSState *env, h= waddr *physical, } } else if (address < 0xC000000000000000ULL) { /* xkphys */ - if (kernel_mode && KX && - (address & 0x07FFFFFFFFFFFFFFULL) <=3D env->PAMask) { - *physical =3D address & env->PAMask; - *prot =3D PAGE_READ | PAGE_WRITE; + if ((address & 0x07FFFFFFFFFFFFFFULL) <=3D env->PAMask) { + /* KX/SX/UX bit to check for each xkphys EVA access mode */ + static const uint8_t am_ksux[8] =3D { + [CP0SC_AM_UK] =3D (1u << CP0St_KX), + [CP0SC_AM_MK] =3D (1u << CP0St_KX), + [CP0SC_AM_MSK] =3D (1u << CP0St_SX), + [CP0SC_AM_MUSK] =3D (1u << CP0St_UX), + [CP0SC_AM_MUSUK] =3D (1u << CP0St_UX), + [CP0SC_AM_USK] =3D (1u << CP0St_SX), + [6] =3D (1u << CP0St_KX), + [CP0SC_AM_UUSK] =3D (1u << CP0St_UX), + }; + unsigned int am =3D CP0SC_AM_UK; + unsigned int xr =3D (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0= SC2_XR; + + if (xr & (1 << ((address >> 59) & 0x7))) { + am =3D (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; + } + /* Does CP0_Status.KX/SX/UX permit the access mode (am) */ + if (env->CP0_Status & am_ksux[am]) { + ret =3D get_seg_physical_address(env, physical, prot, + real_address, rw, access_ty= pe, + mmu_idx, am, false, env->PA= Mask, + 0); + } else { + ret =3D TLBRET_BADADDR; + } } else { ret =3D TLBRET_BADADDR; } @@ -190,35 +309,25 @@ static int get_physical_address (CPUMIPSState *env, h= waddr *physical, #endif } else if (address < (int32_t)KSEG1_BASE) { /* kseg0 */ - if (kernel_mode) { - *physical =3D address - (int32_t)KSEG0_BASE; - *prot =3D PAGE_READ | PAGE_WRITE; - } else { - ret =3D TLBRET_BADADDR; - } + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, rw, + access_type, mmu_idx, + env->CP0_SegCtl1 >> 16, 0x1FFFFF= FF); } else if (address < (int32_t)KSEG2_BASE) { /* kseg1 */ - if (kernel_mode) { - *physical =3D address - (int32_t)KSEG1_BASE; - *prot =3D PAGE_READ | PAGE_WRITE; - } else { - ret =3D TLBRET_BADADDR; - } + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, rw, + access_type, mmu_idx, + env->CP0_SegCtl1, 0x1FFFFFFF); } else if (address < (int32_t)KSEG3_BASE) { /* sseg (kseg2) */ - if (supervisor_mode || kernel_mode) { - ret =3D env->tlb->map_address(env, physical, prot, real_addres= s, rw, access_type); - } else { - ret =3D TLBRET_BADADDR; - } + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, rw, + access_type, mmu_idx, + env->CP0_SegCtl0 >> 16, 0x1FFFFF= FF); } else { /* kseg3 */ /* XXX: debug segment is not emulated */ - if (kernel_mode) { - ret =3D env->tlb->map_address(env, physical, prot, real_addres= s, rw, access_type); - } else { - ret =3D TLBRET_BADADDR; - } + ret =3D get_segctl_physical_address(env, physical, prot, real_addr= ess, rw, + access_type, mmu_idx, + env->CP0_SegCtl0, 0x1FFFFFFF); } return ret; } @@ -722,15 +831,17 @@ void mips_cpu_do_interrupt(CPUState *cs) #if defined(TARGET_MIPS64) int R =3D env->CP0_BadVAddr >> 62; int UX =3D (env->CP0_Status & (1 << CP0St_UX)) !=3D 0; - int SX =3D (env->CP0_Status & (1 << CP0St_SX)) !=3D 0; int KX =3D (env->CP0_Status & (1 << CP0St_KX)) !=3D 0; =20 - if (((R =3D=3D 0 && UX) || (R =3D=3D 1 && SX) || (R =3D=3D 3 &= & KX)) && - (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) + if ((R !=3D 0 || UX) && (R !=3D 3 || KX) && + (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))= ) { offset =3D 0x080; - else + } else { #endif offset =3D 0x000; +#if defined(TARGET_MIPS64) + } +#endif } goto set_EPC; case EXCP_TLBS: @@ -741,15 +852,17 @@ void mips_cpu_do_interrupt(CPUState *cs) #if defined(TARGET_MIPS64) int R =3D env->CP0_BadVAddr >> 62; int UX =3D (env->CP0_Status & (1 << CP0St_UX)) !=3D 0; - int SX =3D (env->CP0_Status & (1 << CP0St_SX)) !=3D 0; int KX =3D (env->CP0_Status & (1 << CP0St_KX)) !=3D 0; =20 - if (((R =3D=3D 0 && UX) || (R =3D=3D 1 && SX) || (R =3D=3D 3 &= & KX)) && - (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))) + if ((R !=3D 0 || UX) && (R !=3D 3 || KX) && + (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)))= ) { offset =3D 0x080; - else + } else { #endif offset =3D 0x000; +#if defined(TARGET_MIPS64) + } +#endif } goto set_EPC; case EXCP_AdEL: --=20 2.7.4