From nobody Tue Feb 10 13:01:39 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500604987427848.4550082455461; Thu, 20 Jul 2017 19:43:07 -0700 (PDT) Received: from localhost ([::1]:40712 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dYNuE-00084i-4u for importer@patchew.org; Thu, 20 Jul 2017 22:43:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40102) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dYNop-0003uW-9M for qemu-devel@nongnu.org; Thu, 20 Jul 2017 22:37:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dYNoo-0007YF-4s for qemu-devel@nongnu.org; Thu, 20 Jul 2017 22:37:31 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:53199) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dYNon-0007XT-Vd for qemu-devel@nongnu.org; Thu, 20 Jul 2017 22:37:30 -0400 Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id C430C6DF294EA; Fri, 21 Jul 2017 03:37:26 +0100 (IST) Received: from hhmipssw204.hh.imgtec.org (10.100.21.121) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Fri, 21 Jul 2017 03:37:28 +0100 From: Yongbok Kim To: Date: Fri, 21 Jul 2017 03:37:10 +0100 Message-ID: <1500604635-15027-10-git-send-email-yongbok.kim@imgtec.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500604635-15027-1-git-send-email-yongbok.kim@imgtec.com> References: <1500604635-15027-1-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [10.100.21.121] X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 195.59.15.196 Subject: [Qemu-devel] [PULL 09/14] target/mips: Abstract mmu_idx from hflags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , James Hogan , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: James Hogan The MIPS mmu_idx is sometimes calculated from hflags without an env pointer available as cpu_mmu_index() requires. Create a common hflags_mmu_index() for the purpose of this calculation which can operate on any hflags, not just with an env pointer, and update cpu_mmu_index() itself and gen_intermediate_code() to use it. Also update debug_post_eret() and helper_mtc0_status() to log the MMU mode with the status change (SM, UM, or nothing for kernel mode) based on cpu_mmu_index() rather than directly testing hflags. This will also allow the logic to be more easily updated when a new MMU mode is added. Signed-off-by: James Hogan Reviewed-by: Yongbok Kim Cc: Aurelien Jarno Signed-off-by: Yongbok Kim --- target/mips/cpu.h | 8 +++++++- target/mips/op_helper.c | 4 ++-- target/mips/translate.c | 2 +- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 2b699a0..3cf1676 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -699,9 +699,15 @@ extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSSt= ate *env); #define MMU_MODE1_SUFFIX _super #define MMU_MODE2_SUFFIX _user #define MMU_USER_IDX 2 + +static inline int hflags_mmu_index(uint32_t hflags) +{ + return hflags & MIPS_HFLAG_KSU; +} + static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch) { - return env->hflags & MIPS_HFLAG_KSU; + return hflags_mmu_index(env->hflags); } =20 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 3b560d9..da1817e 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -1450,7 +1450,7 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulo= ng arg1) old, old & env->CP0_Cause & CP0Ca_IP_mask, val, val & env->CP0_Cause & CP0Ca_IP_mask, env->CP0_Cause); - switch (env->hflags & MIPS_HFLAG_KSU) { + switch (cpu_mmu_index(env, false)) { case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; @@ -2244,7 +2244,7 @@ static void debug_post_eret(CPUMIPSState *env) qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); if (env->hflags & MIPS_HFLAG_DM) qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); - switch (env->hflags & MIPS_HFLAG_KSU) { + switch (cpu_mmu_index(env, false)) { case MIPS_HFLAG_UM: qemu_log(", UM\n"); break; case MIPS_HFLAG_SM: qemu_log(", SM\n"); break; case MIPS_HFLAG_KM: qemu_log("\n"); break; diff --git a/target/mips/translate.c b/target/mips/translate.c index 9787919..4fb8217 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20157,7 +20157,7 @@ void gen_intermediate_code(CPUState *cs, struct Tra= nslationBlock *tb) #ifdef CONFIG_USER_ONLY ctx.mem_idx =3D MIPS_HFLAG_UM; #else - ctx.mem_idx =3D ctx.hflags & MIPS_HFLAG_KSU; + ctx.mem_idx =3D hflags_mmu_index(ctx.hflags); #endif ctx.default_tcg_memop_mask =3D (ctx.insn_flags & ISA_MIPS32R6) ? MO_UNALN : MO_ALIGN; --=20 2.7.4