From nobody Tue Feb 10 05:26:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150052189401218.78084065041446; Wed, 19 Jul 2017 20:38:14 -0700 (PDT) Received: from localhost ([::1]:35923 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY2Hw-0001pA-Ds for importer@patchew.org; Wed, 19 Jul 2017 23:38:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60450) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qV-0001Cd-Dr for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qL-0005sj-Go for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:47 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:41471) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qL-0005sC-8y for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:37 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 1023720B6D; Wed, 19 Jul 2017 23:09:37 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:37 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id C0B3A7E266; Wed, 19 Jul 2017 23:09:36 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=bf7 Z4MUhRjmjfX4o8iIuhspuVYXF0DESLS23Gn0zuOg=; b=O0upYlTePV0nSGQJ8mB 1IHfj5iM8i0sxM0/zJOW6lQovtauwDfSqFIAMINfvJOWJtuW5MxMOourLEm+6hHY KGpO11HPDkJ3qw9Le4AvfXkE2iM4ARAXknnKfrVuYtxzoCByFgianuwbSHSEr7p9 H+oAx0/yZb1Wqzx071SnDX+s= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=bf7Z4MUhRjmjfX4o8iIuhspuVYXF0DESLS23Gn0zu Og=; b=j03aV5VVNrBxNjzjVnxSLmklt8Pw9Vf24Ows87DXN3EFVJze2jf1N6/wj p/X6L1hklf1ptAvBPcJYmWSwcVy/xVajiR34/Nbl4/vOtcVJqi+dSzJv9TMc4d74 fS+NxelqgOW0DO6vXw7KY2PU4i9J8WecqWu8z+zzIyplK3DQQJNJ7L5B8mHbHvCI 9jOj/FjVrTsUQJpXkCsucNiQ7Yp3Kk4dlZhm2foK/ycZlS1c4JNeWH5Gn5vZ3rp9 Y8uBDiiaKbmzVccmj9pv/91vo12zW/Xt7Xl92Il5/q6M6nMuRD0JDezGwC4VYQ0D kFw4LhRjsngv2C6TuRliw8M6onOpA== X-ME-Sender: X-Sasl-enc: +6w/Os5Kgj1okukc0uk8FpCAii7Q6h4fskzTg4+ITCOS 1500520176 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:16 -0400 Message-Id: <1500520169-23367-31-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 30/43] tci: move tci_regs to tcg_qemu_tb_exec's stack X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Groundwork for supporting multiple TCG contexts. Compile-tested for all targets on an x86_64 host. Suggested-by: Richard Henderson Acked-by: Richard Henderson Signed-off-by: Emilio G. Cota --- tcg/tci.c | 552 +++++++++++++++++++++++++++++++---------------------------= ---- 1 file changed, 279 insertions(+), 273 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 4bdc645..f3216c1 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -55,93 +55,95 @@ typedef uint64_t (*helper_function)(tcg_target_ulong, t= cg_target_ulong, tcg_target_ulong); #endif =20 -static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS]; - -static tcg_target_ulong tci_read_reg(TCGReg index) +static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg = index) { - tci_assert(index < ARRAY_SIZE(tci_reg)); - return tci_reg[index]; + tci_assert(index < TCG_TARGET_NB_REGS); + return regs[index]; } =20 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 -static int8_t tci_read_reg8s(TCGReg index) +static int8_t tci_read_reg8s(const tcg_target_ulong *regs, TCGReg index) { - return (int8_t)tci_read_reg(index); + return (int8_t)tci_read_reg(regs, index); } #endif =20 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 -static int16_t tci_read_reg16s(TCGReg index) +static int16_t tci_read_reg16s(const tcg_target_ulong *regs, TCGReg index) { - return (int16_t)tci_read_reg(index); + return (int16_t)tci_read_reg(regs, index); } #endif =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static int32_t tci_read_reg32s(TCGReg index) +static int32_t tci_read_reg32s(const tcg_target_ulong *regs, TCGReg index) { - return (int32_t)tci_read_reg(index); + return (int32_t)tci_read_reg(regs, index); } #endif =20 -static uint8_t tci_read_reg8(TCGReg index) +static uint8_t tci_read_reg8(const tcg_target_ulong *regs, TCGReg index) { - return (uint8_t)tci_read_reg(index); + return (uint8_t)tci_read_reg(regs, index); } =20 -static uint16_t tci_read_reg16(TCGReg index) +static uint16_t tci_read_reg16(const tcg_target_ulong *regs, TCGReg index) { - return (uint16_t)tci_read_reg(index); + return (uint16_t)tci_read_reg(regs, index); } =20 -static uint32_t tci_read_reg32(TCGReg index) +static uint32_t tci_read_reg32(const tcg_target_ulong *regs, TCGReg index) { - return (uint32_t)tci_read_reg(index); + return (uint32_t)tci_read_reg(regs, index); } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static uint64_t tci_read_reg64(TCGReg index) +static uint64_t tci_read_reg64(const tcg_target_ulong *regs, TCGReg index) { - return tci_read_reg(index); + return tci_read_reg(regs, index); } #endif =20 -static void tci_write_reg(TCGReg index, tcg_target_ulong value) +static void +tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value) { - tci_assert(index < ARRAY_SIZE(tci_reg)); + tci_assert(index < TCG_TARGET_NB_REGS); tci_assert(index !=3D TCG_AREG0); tci_assert(index !=3D TCG_REG_CALL_STACK); - tci_reg[index] =3D value; + regs[index] =3D value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 64 -static void tci_write_reg32s(TCGReg index, int32_t value) +static void +tci_write_reg32s(tcg_target_ulong *regs, TCGReg index, int32_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } #endif =20 -static void tci_write_reg8(TCGReg index, uint8_t value) +static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t v= alue) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } =20 -static void tci_write_reg32(TCGReg index, uint32_t value) +static void +tci_write_reg32(tcg_target_ulong *regs, TCGReg index, uint32_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 -static void tci_write_reg64(uint32_t high_index, uint32_t low_index, - uint64_t value) +static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, + uint32_t low_index, uint64_t value) { - tci_write_reg(low_index, value); - tci_write_reg(high_index, value >> 32); + tci_write_reg(regs, low_index, value); + tci_write_reg(regs, high_index, value >> 32); } #elif TCG_TARGET_REG_BITS =3D=3D 64 -static void tci_write_reg64(TCGReg index, uint64_t value) +static void +tci_write_reg64(tcg_target_ulong *regs, TCGReg index, uint64_t value) { - tci_write_reg(index, value); + tci_write_reg(regs, index, value); } #endif =20 @@ -188,94 +190,97 @@ static uint64_t tci_read_i64(uint8_t **tb_ptr) #endif =20 /* Read indexed register (native size) from bytecode. */ -static tcg_target_ulong tci_read_r(uint8_t **tb_ptr) +static tcg_target_ulong +tci_read_r(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - tcg_target_ulong value =3D tci_read_reg(**tb_ptr); + tcg_target_ulong value =3D tci_read_reg(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 /* Read indexed register (8 bit) from bytecode. */ -static uint8_t tci_read_r8(uint8_t **tb_ptr) +static uint8_t tci_read_r8(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - uint8_t value =3D tci_read_reg8(**tb_ptr); + uint8_t value =3D tci_read_reg8(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 /* Read indexed register (8 bit signed) from bytecode. */ -static int8_t tci_read_r8s(uint8_t **tb_ptr) +static int8_t tci_read_r8s(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - int8_t value =3D tci_read_reg8s(**tb_ptr); + int8_t value =3D tci_read_reg8s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register (16 bit) from bytecode. */ -static uint16_t tci_read_r16(uint8_t **tb_ptr) +static uint16_t tci_read_r16(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint16_t value =3D tci_read_reg16(**tb_ptr); + uint16_t value =3D tci_read_reg16(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 /* Read indexed register (16 bit signed) from bytecode. */ -static int16_t tci_read_r16s(uint8_t **tb_ptr) +static int16_t tci_read_r16s(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - int16_t value =3D tci_read_reg16s(**tb_ptr); + int16_t value =3D tci_read_reg16s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register (32 bit) from bytecode. */ -static uint32_t tci_read_r32(uint8_t **tb_ptr) +static uint32_t tci_read_r32(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint32_t value =3D tci_read_reg32(**tb_ptr); + uint32_t value =3D tci_read_reg32(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 /* Read two indexed registers (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_r64(uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint32_t low =3D tci_read_r32(tb_ptr); - return tci_uint64(tci_read_r32(tb_ptr), low); + uint32_t low =3D tci_read_r32(regs, tb_ptr); + return tci_uint64(tci_read_r32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register (32 bit signed) from bytecode. */ -static int32_t tci_read_r32s(uint8_t **tb_ptr) +static int32_t tci_read_r32s(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - int32_t value =3D tci_read_reg32s(**tb_ptr); + int32_t value =3D tci_read_reg32s(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } =20 /* Read indexed register (64 bit) from bytecode. */ -static uint64_t tci_read_r64(uint8_t **tb_ptr) +static uint64_t tci_read_r64(const tcg_target_ulong *regs, uint8_t **tb_pt= r) { - uint64_t value =3D tci_read_reg64(**tb_ptr); + uint64_t value =3D tci_read_reg64(regs, **tb_ptr); *tb_ptr +=3D 1; return value; } #endif =20 /* Read indexed register(s) with target address from bytecode. */ -static target_ulong tci_read_ulong(uint8_t **tb_ptr) +static target_ulong +tci_read_ulong(const tcg_target_ulong *regs, uint8_t **tb_ptr) { - target_ulong taddr =3D tci_read_r(tb_ptr); + target_ulong taddr =3D tci_read_r(regs, tb_ptr); #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS - taddr +=3D (uint64_t)tci_read_r(tb_ptr) << 32; + taddr +=3D (uint64_t)tci_read_r(regs, tb_ptr) << 32; #endif return taddr; } =20 /* Read indexed register or constant (native size) from bytecode. */ -static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) +static tcg_target_ulong +tci_read_ri(const tcg_target_ulong *regs, uint8_t **tb_ptr) { tcg_target_ulong value; TCGReg r =3D **tb_ptr; @@ -283,13 +288,13 @@ static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i(tb_ptr); } else { - value =3D tci_read_reg(r); + value =3D tci_read_reg(regs, r); } return value; } =20 /* Read indexed register or constant (32 bit) from bytecode. */ -static uint32_t tci_read_ri32(uint8_t **tb_ptr) +static uint32_t tci_read_ri32(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { uint32_t value; TCGReg r =3D **tb_ptr; @@ -297,21 +302,21 @@ static uint32_t tci_read_ri32(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i32(tb_ptr); } else { - value =3D tci_read_reg32(r); + value =3D tci_read_reg32(regs, r); } return value; } =20 #if TCG_TARGET_REG_BITS =3D=3D 32 /* Read two indexed registers or constants (2 * 32 bit) from bytecode. */ -static uint64_t tci_read_ri64(uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { - uint32_t low =3D tci_read_ri32(tb_ptr); - return tci_uint64(tci_read_ri32(tb_ptr), low); + uint32_t low =3D tci_read_ri32(regs, tb_ptr); + return tci_uint64(tci_read_ri32(regs, tb_ptr), low); } #elif TCG_TARGET_REG_BITS =3D=3D 64 /* Read indexed register or constant (64 bit) from bytecode. */ -static uint64_t tci_read_ri64(uint8_t **tb_ptr) +static uint64_t tci_read_ri64(const tcg_target_ulong *regs, uint8_t **tb_p= tr) { uint64_t value; TCGReg r =3D **tb_ptr; @@ -319,7 +324,7 @@ static uint64_t tci_read_ri64(uint8_t **tb_ptr) if (r =3D=3D TCG_CONST) { value =3D tci_read_i64(tb_ptr); } else { - value =3D tci_read_reg64(r); + value =3D tci_read_reg64(regs, r); } return value; } @@ -465,12 +470,13 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, T= CGCond condition) /* Interpret pseudo code in tb. */ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) { + tcg_target_ulong regs[TCG_TARGET_NB_REGS]; long tcg_temps[CPU_TEMP_BUF_NLONGS]; uintptr_t sp_value =3D (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS); uintptr_t ret =3D 0; =20 - tci_reg[TCG_AREG0] =3D (tcg_target_ulong)env; - tci_reg[TCG_REG_CALL_STACK] =3D sp_value; + regs[TCG_AREG0] =3D (tcg_target_ulong)env; + regs[TCG_REG_CALL_STACK] =3D sp_value; tci_assert(tb_ptr); =20 for (;;) { @@ -503,27 +509,27 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 switch (opc) { case INDEX_op_call: - t0 =3D tci_read_ri(&tb_ptr); + t0 =3D tci_read_ri(regs, &tb_ptr); #if TCG_TARGET_REG_BITS =3D=3D 32 - tmp64 =3D ((helper_function)t0)(tci_read_reg(TCG_REG_R0), - tci_read_reg(TCG_REG_R1), - tci_read_reg(TCG_REG_R2), - tci_read_reg(TCG_REG_R3), - tci_read_reg(TCG_REG_R5), - tci_read_reg(TCG_REG_R6), - tci_read_reg(TCG_REG_R7), - tci_read_reg(TCG_REG_R8), - tci_read_reg(TCG_REG_R9), - tci_read_reg(TCG_REG_R10)); - tci_write_reg(TCG_REG_R0, tmp64); - tci_write_reg(TCG_REG_R1, tmp64 >> 32); + tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R5), + tci_read_reg(regs, TCG_REG_R6), + tci_read_reg(regs, TCG_REG_R7), + tci_read_reg(regs, TCG_REG_R8), + tci_read_reg(regs, TCG_REG_R9), + tci_read_reg(regs, TCG_REG_R10)); + tci_write_reg(regs, TCG_REG_R0, tmp64); + tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); #else - tmp64 =3D ((helper_function)t0)(tci_read_reg(TCG_REG_R0), - tci_read_reg(TCG_REG_R1), - tci_read_reg(TCG_REG_R2), - tci_read_reg(TCG_REG_R3), - tci_read_reg(TCG_REG_R5)); - tci_write_reg(TCG_REG_R0, tmp64); + tmp64 =3D ((helper_function)t0)(tci_read_reg(regs, TCG_REG_R0), + tci_read_reg(regs, TCG_REG_R1), + tci_read_reg(regs, TCG_REG_R2), + tci_read_reg(regs, TCG_REG_R3), + tci_read_reg(regs, TCG_REG_R5)); + tci_write_reg(regs, TCG_REG_R0, tmp64); #endif break; case INDEX_op_br: @@ -533,46 +539,46 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) continue; case INDEX_op_setcond_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg32(t0, tci_compare32(t1, t2, condition)); + tci_write_reg32(regs, t0, tci_compare32(t1, t2, condition)); break; #if TCG_TARGET_REG_BITS =3D=3D 32 case INDEX_op_setcond2_i32: t0 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - v64 =3D tci_read_ri64(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + v64 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg32(t0, tci_compare64(tmp64, v64, condition)); + tci_write_reg32(regs, t0, tci_compare64(tmp64, v64, condition)= ); break; #elif TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_setcond_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; - tci_write_reg64(t0, tci_compare64(t1, t2, condition)); + tci_write_reg64(regs, t0, tci_compare64(t1, t2, condition)); break; #endif case INDEX_op_mov_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; case INDEX_op_movi_i32: t0 =3D *tb_ptr++; t1 =3D tci_read_i32(&tb_ptr); - tci_write_reg32(t0, t1); + tci_write_reg32(regs, t0, t1); break; =20 /* Load/store operations (32 bit). */ =20 case INDEX_op_ld8u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg8(t0, *(uint8_t *)(t1 + t2)); + tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i32: case INDEX_op_ld16u_i32: @@ -583,25 +589,25 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) break; case INDEX_op_ld_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32(t0, *(uint32_t *)(t1 + t2)); + tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2)); break; case INDEX_op_st8_i32: - t0 =3D tci_read_r8(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r8(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; case INDEX_op_st16_i32: - t0 =3D tci_read_r16(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i32: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_assert(t1 !=3D sp_value || (int32_t)t2 < 0); *(uint32_t *)(t1 + t2) =3D t0; @@ -611,46 +617,46 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 case INDEX_op_add_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 + t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 + t2); break; case INDEX_op_sub_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 - t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 - t2); break; case INDEX_op_mul_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 * t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i32 case INDEX_op_div_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (int32_t)t1 / (int32_t)t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, (int32_t)t1 / (int32_t)t2); break; case INDEX_op_divu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 / t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 / t2); break; case INDEX_op_rem_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (int32_t)t1 % (int32_t)t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, (int32_t)t1 % (int32_t)t2); break; case INDEX_op_remu_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 % t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 % t2); break; #elif TCG_TARGET_HAS_div2_i32 case INDEX_op_div2_i32: @@ -660,71 +666,71 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) #endif case INDEX_op_and_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 & t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 & t2); break; case INDEX_op_or_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 | t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 | t2); break; case INDEX_op_xor_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 ^ t2); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 ^ t2); break; =20 /* Shift/rotate operations (32 bit). */ =20 case INDEX_op_shl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 << (t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 << (t2 & 31)); break; case INDEX_op_shr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, t1 >> (t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1 >> (t2 & 31)); break; case INDEX_op_sar_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, ((int32_t)t1 >> (t2 & 31))); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ((int32_t)t1 >> (t2 & 31))); break; #if TCG_TARGET_HAS_rot_i32 case INDEX_op_rotl_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, rol32(t1, t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, rol32(t1, t2 & 31)); break; case INDEX_op_rotr_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri32(&tb_ptr); - t2 =3D tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, ror32(t1, t2 & 31)); + t1 =3D tci_read_ri32(regs, &tb_ptr); + t2 =3D tci_read_ri32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ror32(t1, t2 & 31)); break; #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - t2 =3D tci_read_r32(&tb_ptr); + t1 =3D tci_read_r32(regs, &tb_ptr); + t2 =3D tci_read_r32(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp32 =3D (((1 << tmp8) - 1) << tmp16); - tci_write_reg32(t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32)); + tci_write_reg32(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp= 32)); break; #endif case INDEX_op_brcond_i32: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_ri32(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_ri32(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare32(t0, t1, condition)) { @@ -737,20 +743,20 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) case INDEX_op_add2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - tmp64 +=3D tci_read_r64(&tb_ptr); - tci_write_reg64(t1, t0, tmp64); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + tmp64 +=3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_sub2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - tmp64 =3D tci_read_r64(&tb_ptr); - tmp64 -=3D tci_read_r64(&tb_ptr); - tci_write_reg64(t1, t0, tmp64); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + tmp64 -=3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, tmp64); break; case INDEX_op_brcond2_i32: - tmp64 =3D tci_read_r64(&tb_ptr); - v64 =3D tci_read_ri64(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + v64 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(tmp64, v64, condition)) { @@ -762,86 +768,86 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) case INDEX_op_mulu2_i32: t0 =3D *tb_ptr++; t1 =3D *tb_ptr++; - t2 =3D tci_read_r32(&tb_ptr); - tmp64 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t1, t0, t2 * tmp64); + t2 =3D tci_read_r32(regs, &tb_ptr); + tmp64 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t1, t0, t2 * tmp64); break; #endif /* TCG_TARGET_REG_BITS =3D=3D 32 */ #if TCG_TARGET_HAS_ext8s_i32 case INDEX_op_ext8s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r8s(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i32 case INDEX_op_ext16s_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r16s(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8u_i32 case INDEX_op_ext8u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r8(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i32 case INDEX_op_ext16u_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg32(t0, t1); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg32(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_bswap16_i32 case INDEX_op_bswap16_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg32(t0, bswap16(t1)); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg32(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i32 case INDEX_op_bswap32_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, bswap32(t1)); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_not_i32 case INDEX_op_not_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, ~t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i32 case INDEX_op_neg_i32: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg32(t0, -t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg32(regs, t0, -t1); break; #endif #if TCG_TARGET_REG_BITS =3D=3D 64 case INDEX_op_mov_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; case INDEX_op_movi_i64: t0 =3D *tb_ptr++; t1 =3D tci_read_i64(&tb_ptr); - tci_write_reg64(t0, t1); + tci_write_reg64(regs, t0, t1); break; =20 /* Load/store operations (64 bit). */ =20 case INDEX_op_ld8u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg8(t0, *(uint8_t *)(t1 + t2)); + tci_write_reg8(regs, t0, *(uint8_t *)(t1 + t2)); break; case INDEX_op_ld8s_i64: case INDEX_op_ld16u_i64: @@ -850,43 +856,43 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) break; case INDEX_op_ld32u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32(t0, *(uint32_t *)(t1 + t2)); + tci_write_reg32(regs, t0, *(uint32_t *)(t1 + t2)); break; case INDEX_op_ld32s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg32s(t0, *(int32_t *)(t1 + t2)); + tci_write_reg32s(regs, t0, *(int32_t *)(t1 + t2)); break; case INDEX_op_ld_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r(&tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); - tci_write_reg64(t0, *(uint64_t *)(t1 + t2)); + tci_write_reg64(regs, t0, *(uint64_t *)(t1 + t2)); break; case INDEX_op_st8_i64: - t0 =3D tci_read_r8(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r8(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint8_t *)(t1 + t2) =3D t0; break; case INDEX_op_st16_i64: - t0 =3D tci_read_r16(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r16(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint16_t *)(t1 + t2) =3D t0; break; case INDEX_op_st32_i64: - t0 =3D tci_read_r32(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r32(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); *(uint32_t *)(t1 + t2) =3D t0; break; case INDEX_op_st_i64: - t0 =3D tci_read_r64(&tb_ptr); - t1 =3D tci_read_r(&tb_ptr); + t0 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_r(regs, &tb_ptr); t2 =3D tci_read_s32(&tb_ptr); tci_assert(t1 !=3D sp_value || (int32_t)t2 < 0); *(uint64_t *)(t1 + t2) =3D t0; @@ -896,21 +902,21 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) =20 case INDEX_op_add_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 + t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 + t2); break; case INDEX_op_sub_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 - t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 - t2); break; case INDEX_op_mul_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 * t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 * t2); break; #if TCG_TARGET_HAS_div_i64 case INDEX_op_div_i64: @@ -927,71 +933,71 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) #endif case INDEX_op_and_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 & t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 & t2); break; case INDEX_op_or_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 | t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 | t2); break; case INDEX_op_xor_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 ^ t2); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 ^ t2); break; =20 /* Shift/rotate operations (64 bit). */ =20 case INDEX_op_shl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 << (t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 << (t2 & 63)); break; case INDEX_op_shr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, t1 >> (t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1 >> (t2 & 63)); break; case INDEX_op_sar_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, ((int64_t)t1 >> (t2 & 63))); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ((int64_t)t1 >> (t2 & 63))); break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, rol64(t1, t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, rol64(t1, t2 & 63)); break; case INDEX_op_rotr_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_ri64(&tb_ptr); - t2 =3D tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, ror64(t1, t2 & 63)); + t1 =3D tci_read_ri64(regs, &tb_ptr); + t2 =3D tci_read_ri64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ror64(t1, t2 & 63)); break; #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - t2 =3D tci_read_r64(&tb_ptr); + t1 =3D tci_read_r64(regs, &tb_ptr); + t2 =3D tci_read_r64(regs, &tb_ptr); tmp16 =3D *tb_ptr++; tmp8 =3D *tb_ptr++; tmp64 =3D (((1ULL << tmp8) - 1) << tmp16); - tci_write_reg64(t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64)); + tci_write_reg64(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp= 64)); break; #endif case INDEX_op_brcond_i64: - t0 =3D tci_read_r64(&tb_ptr); - t1 =3D tci_read_ri64(&tb_ptr); + t0 =3D tci_read_r64(regs, &tb_ptr); + t1 =3D tci_read_ri64(regs, &tb_ptr); condition =3D *tb_ptr++; label =3D tci_read_label(&tb_ptr); if (tci_compare64(t0, t1, condition)) { @@ -1003,29 +1009,29 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) #if TCG_TARGET_HAS_ext8u_i64 case INDEX_op_ext8u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r8(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext8s_i64 case INDEX_op_ext8s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r8s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r8s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16s_i64 case INDEX_op_ext16s_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r16s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext16u_i64 case INDEX_op_ext16u_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #endif #if TCG_TARGET_HAS_ext32s_i64 @@ -1033,51 +1039,51 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) #endif case INDEX_op_ext_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32s(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r32s(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #if TCG_TARGET_HAS_ext32u_i64 case INDEX_op_ext32u_i64: #endif case INDEX_op_extu_i32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t0, t1); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t0, t1); break; #if TCG_TARGET_HAS_bswap16_i64 case INDEX_op_bswap16_i64: TODO(); t0 =3D *tb_ptr++; - t1 =3D tci_read_r16(&tb_ptr); - tci_write_reg64(t0, bswap16(t1)); + t1 =3D tci_read_r16(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap16(t1)); break; #endif #if TCG_TARGET_HAS_bswap32_i64 case INDEX_op_bswap32_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r32(&tb_ptr); - tci_write_reg64(t0, bswap32(t1)); + t1 =3D tci_read_r32(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap32(t1)); break; #endif #if TCG_TARGET_HAS_bswap64_i64 case INDEX_op_bswap64_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, bswap64(t1)); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, bswap64(t1)); break; #endif #if TCG_TARGET_HAS_not_i64 case INDEX_op_not_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, ~t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, ~t1); break; #endif #if TCG_TARGET_HAS_neg_i64 case INDEX_op_neg_i64: t0 =3D *tb_ptr++; - t1 =3D tci_read_r64(&tb_ptr); - tci_write_reg64(t0, -t1); + t1 =3D tci_read_r64(regs, &tb_ptr); + tci_write_reg64(regs, t0, -t1); break; #endif #endif /* TCG_TARGET_REG_BITS =3D=3D 64 */ @@ -1098,7 +1104,7 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) continue; case INDEX_op_qemu_ld_i32: t0 =3D *tb_ptr++; - taddr =3D tci_read_ulong(&tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -1128,14 +1134,14 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) default: tcg_abort(); } - tci_write_reg(t0, tmp32); + tci_write_reg(regs, t0, tmp32); break; case INDEX_op_qemu_ld_i64: t0 =3D *tb_ptr++; if (TCG_TARGET_REG_BITS =3D=3D 32) { t1 =3D *tb_ptr++; } - taddr =3D tci_read_ulong(&tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SSIZE)) { case MO_UB: @@ -1177,14 +1183,14 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8= _t *tb_ptr) default: tcg_abort(); } - tci_write_reg(t0, tmp64); + tci_write_reg(regs, t0, tmp64); if (TCG_TARGET_REG_BITS =3D=3D 32) { - tci_write_reg(t1, tmp64 >> 32); + tci_write_reg(regs, t1, tmp64 >> 32); } break; case INDEX_op_qemu_st_i32: - t0 =3D tci_read_r(&tb_ptr); - taddr =3D tci_read_ulong(&tb_ptr); + t0 =3D tci_read_r(regs, &tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: @@ -1207,8 +1213,8 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t= *tb_ptr) } break; case INDEX_op_qemu_st_i64: - tmp64 =3D tci_read_r64(&tb_ptr); - taddr =3D tci_read_ulong(&tb_ptr); + tmp64 =3D tci_read_r64(regs, &tb_ptr); + taddr =3D tci_read_ulong(regs, &tb_ptr); oi =3D tci_read_i(&tb_ptr); switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { case MO_UB: --=20 2.7.4