From nobody Mon Feb 9 09:28:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500520944321189.61391506492964; Wed, 19 Jul 2017 20:22:24 -0700 (PDT) Received: from localhost ([::1]:35850 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY22g-00052y-IM for importer@patchew.org; Wed, 19 Jul 2017 23:22:22 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60180) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qN-00016V-5B for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005qv-R7 for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:39 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:40131) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005pO-Jl for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 2E8F820B50; Wed, 19 Jul 2017 23:09:35 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:35 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id E15B37E057; Wed, 19 Jul 2017 23:09:34 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=0J/ gSaSYrTzVwre/A1lgzU2x4Qb/KiCcXMpXc4/SU8g=; b=f0v0XOIltCp2CWHv//8 U/wcKiFy3QeVX9dm1xrMv3D5oBFSqNH0i6H2V0jaGI/WIu0HYlEeejmXVBPM9yFL AwyTJAObVLK5gZRIemj0F4eyW/JWdITY7bmeVzirofKktIzQD4evsmX6CMtFq9hO utgX6h8/4H7po63EQRQ/Ktxc= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=0J/gSaSYrTzVwre/A1lgzU2x4Qb/KiCcXMpXc4/SU 8g=; b=DOCPxUaHiWOsA7haRRWqLRQPOMwJOgbTJjq4De8tcpv9HDdmkPaY1HSBo l1lbUUjocxIONmsR88BauoXpM5Rw0IAxe4MbzKvHOtcudbNq5J5KhUPn4m/gXxpc mOR4QWpR2ti0+5UoHBrc/RvT8E5neLxKe/9JNnZ3wWecdY5ilCUh/5ITL0Izl2R/ 2nVOV7VtqhQPXDHLhzOQUqzNZCkcpPX9tGlXV7g+JeV+Hg+pbz24Lrn+LOHenMrv 0fNIga6dCVpBhOxkIEInT7kyZitH6H1SZ4eHbPWdkg7wnsxXgob0fX1NWWcYeXUf 1PvCMJ9cJqQAzPeK9vm3r/OToNglw== X-ME-Sender: X-Sasl-enc: W2+vgeAMLE5GmT01/tRpwML6KaLTk+nBUBJOmrlX2jh0 1500520174 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:09:06 -0400 Message-Id: <1500520169-23367-21-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 20/43] tcg: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. The tb->cflags field is not passed to tcg generation functions. So we add a bit to TCGContext, storing there whether CF_PARALLEL is set before translating every TB. Most architectures have <=3D 32 registers, which results in a 4-byte hole in TCGContext. Use this hole for the bit we need, which we store in a bool. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- tcg/tcg.h | 1 + accel/tcg/translate-all.c | 1 + tcg/tcg-op.c | 10 +++++----- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 96872f8..9b6dade 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -656,6 +656,7 @@ struct TCGContext { uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_addr if !USE_DIRECT_J= UMP */ =20 TCGRegSet reserved_regs; + bool cf_parallel; /* whether CF_PARALLEL is set in tb->cflags */ intptr_t current_frame_offset; intptr_t frame_start; intptr_t frame_end; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 600c0a1..645bc70 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1271,6 +1271,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb->flags =3D flags; tb->cflags =3D cflags; tb->trace_vcpu_dstate =3D *cpu->trace_dstate; + tcg_ctx.cf_parallel =3D !!(cflags & CF_PARALLEL); =20 #ifdef CONFIG_PROFILER tcg_ctx.tb_count1++; /* includes aborted translations because of diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 205d07f..ef420d4 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -150,7 +150,7 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg= a1, TCGArg a2, =20 void tcg_gen_mb(TCGBar mb_type) { - if (parallel_cpus) { + if (tcg_ctx.cf_parallel) { tcg_gen_op1(&tcg_ctx, INDEX_op_mb, mb_type); } } @@ -2794,7 +2794,7 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv a= ddr, TCGv_i32 cmpv, { memop =3D tcg_canonicalize_memop(memop, 0, 0); =20 - if (!parallel_cpus) { + if (!tcg_ctx.cf_parallel) { TCGv_i32 t1 =3D tcg_temp_new_i32(); TCGv_i32 t2 =3D tcg_temp_new_i32(); =20 @@ -2838,7 +2838,7 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv a= ddr, TCGv_i64 cmpv, { memop =3D tcg_canonicalize_memop(memop, 1, 0); =20 - if (!parallel_cpus) { + if (!tcg_ctx.cf_parallel) { TCGv_i64 t1 =3D tcg_temp_new_i64(); TCGv_i64 t2 =3D tcg_temp_new_i64(); =20 @@ -3015,7 +3015,7 @@ static void * const table_##NAME[16] =3D { = \ void tcg_gen_atomic_##NAME##_i32 \ (TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \ { \ - if (parallel_cpus) { \ + if (tcg_ctx.cf_parallel) { \ do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \ @@ -3025,7 +3025,7 @@ void tcg_gen_atomic_##NAME##_i32 = \ void tcg_gen_atomic_##NAME##_i64 \ (TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \ { \ - if (parallel_cpus) { \ + if (tcg_ctx.cf_parallel) { \ do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \ } else { \ do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \ --=20 2.7.4