From nobody Mon Feb 9 18:17:45 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150052078635737.83624945530187; Wed, 19 Jul 2017 20:19:46 -0700 (PDT) Received: from localhost ([::1]:35836 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY208-0001jY-IU for importer@patchew.org; Wed, 19 Jul 2017 23:19:44 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60151) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dY1qM-00016Q-CQ for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dY1qJ-0005pr-HX for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:38 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:40143) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dY1qJ-0005od-7f for qemu-devel@nongnu.org; Wed, 19 Jul 2017 23:09:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id D1B9320A5D; Wed, 19 Jul 2017 23:09:33 -0400 (EDT) Received: from frontend2 ([10.202.2.161]) by compute4.internal (MEProxy); Wed, 19 Jul 2017 23:09:33 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 94BC3240AF; Wed, 19 Jul 2017 23:09:33 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=XLG X7+ueAlf3sv88oU1zL+yCry8RTn251OXHxfYcG3Q=; b=n0kZ40kXO9VWm/8hKqf Y4erSuVK1qXr+XN35FWEe0oDQlJulWckxgn8oRfVLVzKpLGEP7hD7dYC8UaKvg0S NTuANMVIijKeWd9YHK7BH553FBvyah8fqN5spyuKKvG/sEJiuS1docu61PhFaaNe Q04DTK/59kU+RGr1LqAM+v18= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=XLGX7+ueAlf3sv88oU1zL+yCry8RTn251OXHxfYcG 3Q=; b=EMv4Q0Sx4J9lPb+JcCbBj/KAxWLrnn5itSyUVsxMwuvo/AM5UKaUYhXq+ 3jEuVEspFZHGUZTQ9uxPTNaTJDy+ByZ6m42JrchqIr2w0wB9FbNRO4H2CHcdGuMq 28fc7V+yVPBRbboLpOs7J/34GQIwVeFCXBjIsQX9xDPx3qZuZXCxBPznz4wzeTxu k0tlAJe9J3Z49BOcJn9V5jc86xchR91g6gtHzlExoSQtHQRZRmqR74jOlKjFxk1g B3MTPHiDIrB6mbeGFlJR7ujVjTC4RkDp041yJoQ5hbrPDJmuGnCrd2Ps4uU+CIBw 8Sn+w+LR5tmmsHmwF6n/vtOzQyaEQ== X-ME-Sender: X-Sasl-enc: u8i+05w2jyl+C91ElZX23Jgnw0wMnFY285I83YMIfTlV 1500520173 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Wed, 19 Jul 2017 23:08:59 -0400 Message-Id: <1500520169-23367-14-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500520169-23367-1-git-send-email-cota@braap.org> References: <1500520169-23367-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v3 13/43] target/arm: check CF_PARALLEL instead of parallel_cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Thereby decoupling the resulting translated code from the current state of the system. Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota --- target/arm/helper-a64.h | 4 ++++ target/arm/helper-a64.c | 38 ++++++++++++++++++++++++++++++++------ target/arm/op_helper.c | 7 ------- target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------ target/arm/translate.c | 9 +++++++-- 5 files changed, 68 insertions(+), 21 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 6f9eaba..85d8674 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -43,4 +43,8 @@ DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32= , f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) +DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG, + i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64= , i64) +DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG, + i64, env, i64, i64, i64) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index d9df82c..d0e435c 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -430,8 +430,9 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, = uint32_t bytes) } =20 /* Returns 0 on success; 1 otherwise. */ -uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) +static uint64_t do_paired_cmpxchg64_le(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi, + bool parallel) { uintptr_t ra =3D GETPC(); Int128 oldv, cmpv, newv; @@ -440,7 +441,7 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, = uint64_t addr, cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); newv =3D int128_make128(new_lo, new_hi); =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -484,8 +485,21 @@ uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env,= uint64_t addr, return !success; } =20 -uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) +uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t ne= w_hi) +{ + return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, false); +} + +uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t a= ddr, + uint64_t new_lo, uint64_t ne= w_hi) +{ + return do_paired_cmpxchg64_le(env, addr, new_lo, new_hi, true); +} + +static uint64_t do_paired_cmpxchg64_be(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi, + bool parallel) { uintptr_t ra =3D GETPC(); Int128 oldv, cmpv, newv; @@ -494,7 +508,7 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, = uint64_t addr, cmpv =3D int128_make128(env->exclusive_val, env->exclusive_high); newv =3D int128_make128(new_lo, new_hi); =20 - if (parallel_cpus) { + if (parallel) { #ifndef CONFIG_ATOMIC128 cpu_loop_exit_atomic(ENV_GET_CPU(env), ra); #else @@ -537,3 +551,15 @@ uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env,= uint64_t addr, =20 return !success; } + +uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, + uint64_t new_lo, uint64_t new_hi) +{ + return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, false); +} + +uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t a= ddr, + uint64_t new_lo, uint64_t new_hi) +{ + return do_paired_cmpxchg64_be(env, addr, new_lo, new_hi, true); +} diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 2a85666..a28f254 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -450,13 +450,6 @@ void HELPER(yield)(CPUARMState *env) ARMCPU *cpu =3D arm_env_get_cpu(env); CPUState *cs =3D CPU(cpu); =20 - /* When running in MTTCG we don't generate jumps to the yield and - * WFE helpers as it won't affect the scheduling of other vCPUs. - * If we wanted to more completely model WFE/SEV so we don't busy - * spin unnecessarily we would need to do something more involved. - */ - g_assert(!parallel_cpus); - /* This is a non-trappable hint instruction that generally indicates * that the guest is currently busy-looping. Yield control back to the * top level loop so that a more deserving VCPU has a chance to run. diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 685f1b0..5e775bd 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1334,13 +1334,18 @@ static void handle_hint(DisasContext *s, uint32_t i= nsn, case 3: /* WFI */ s->is_jmp =3D DISAS_WFI; return; + /* When running in MTTCG we don't generate jumps to the yield and + * WFE helpers as it won't affect the scheduling of other vCPUs. + * If we wanted to more completely model WFE/SEV so we don't busy + * spin unnecessarily we would need to do something more involved. + */ case 1: /* YIELD */ - if (!parallel_cpus) { + if (!(tb_cflags(s->tb) & CF_PARALLEL)) { s->is_jmp =3D DISAS_YIELD; } return; case 2: /* WFE */ - if (!parallel_cpus) { + if (!(tb_cflags(s->tb) & CF_PARALLEL)) { s->is_jmp =3D DISAS_WFE; } return; @@ -1918,11 +1923,25 @@ static void gen_store_exclusive(DisasContext *s, in= t rd, int rt, int rt2, tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); tcg_temp_free_i64(val); } else if (s->be_data =3D=3D MO_LE) { - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, cpu_reg(s, = rt), - cpu_reg(s, rt2)); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, addr, + cpu_reg(s, rt), + cpu_reg(s, rt2)); + } else { + gen_helper_paired_cmpxchg64_le(tmp, cpu_env, addr, + cpu_reg(s, rt), + cpu_reg(s, rt2)); + } } else { - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, cpu_reg(s, = rt), - cpu_reg(s, rt2)); + if (tb_cflags(s->tb) & CF_PARALLEL) { + gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, addr, + cpu_reg(s, rt), + cpu_reg(s, rt2)); + } else { + gen_helper_paired_cmpxchg64_be(tmp, cpu_env, addr, + cpu_reg(s, rt), + cpu_reg(s, rt2)); + } } } else { TCGv_i64 val =3D cpu_reg(s, rt); diff --git a/target/arm/translate.c b/target/arm/translate.c index ccfb428..bd0ef58 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4497,8 +4497,13 @@ static void gen_exception_return(DisasContext *s, TC= Gv_i32 pc) static void gen_nop_hint(DisasContext *s, int val) { switch (val) { + /* When running in MTTCG we don't generate jumps to the yield and + * WFE helpers as it won't affect the scheduling of other vCPUs. + * If we wanted to more completely model WFE/SEV so we don't busy + * spin unnecessarily we would need to do something more involved. + */ case 1: /* yield */ - if (!parallel_cpus) { + if (!(tb_cflags(s->tb) & CF_PARALLEL)) { gen_set_pc_im(s, s->pc); s->is_jmp =3D DISAS_YIELD; } @@ -4508,7 +4513,7 @@ static void gen_nop_hint(DisasContext *s, int val) s->is_jmp =3D DISAS_WFI; break; case 2: /* wfe */ - if (!parallel_cpus) { + if (!(tb_cflags(s->tb) & CF_PARALLEL)) { gen_set_pc_im(s, s->pc); s->is_jmp =3D DISAS_WFE; } --=20 2.7.4