From nobody Mon Feb 9 16:18:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500235750329171.02998649453082; Sun, 16 Jul 2017 13:09:10 -0700 (PDT) Received: from localhost ([::1]:46717 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpqm-0004ZT-Rq for importer@patchew.org; Sun, 16 Jul 2017 16:09:08 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46119) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dWpmZ-0001Af-05 for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dWpmU-0008Gc-Ef for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:46 -0400 Received: from out1-smtp.messagingengine.com ([66.111.4.25]:36725) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dWpmU-0008FJ-6c for qemu-devel@nongnu.org; Sun, 16 Jul 2017 16:04:42 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 58A4320A41; Sun, 16 Jul 2017 16:04:40 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 16 Jul 2017 16:04:40 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id 15F387E1FC; Sun, 16 Jul 2017 16:04:40 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to:x-me-sender :x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=buHV2ud6KIgEkQM wGqy38a8ZRqf0F8XaW5hA3j+ERtU=; b=jZbOHpgvlc3Q5Z11PTh8AHX0U3BnO1g qaOrnC0u4wsjXp6fUB0VzMkOCAfPsER3UqhuwYcnISELiXCH0KjmZS+6zZvPAjy/ zIWyvSK2vFwxTvXlHg9uqbx0Rz6nGbqsnJSIdlgP7Jbm9BziOAen5IG1QMuG/npE ETTYojeFe+QQ= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:content-transfer-encoding:content-type :date:from:in-reply-to:message-id:mime-version:references :subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s= fm1; bh=buHV2ud6KIgEkQMwGqy38a8ZRqf0F8XaW5hA3j+ERtU=; b=KmG9jH1f HvjGqD8aYVxAV1j+/5T2vTtkbEgndW+acIMjc7yjSYwsKSP62Vx/zODXcbLVyVbj xyCi4clQm6qmeDa6RIGcJxF8yQs2lbEDDHGkGDCUjXlOW7ID9cT7AOJu2Di4iRyJ sqkZLfVtlZ071S2jEtJq8gL6gtQTv/SNIuy93Ayg/mHO3vCiCiGsTiVFKQlwpx9Q 8N1zwWI0jNOGsArw/GeTEWvbEcDklY+4tTWccEjA0RqeGO+BOv6NOLlacD/8rq7f xfmQkFOLUPrAtqjMm3mpvb7o7AmAz3Bqv94/YpM9OlFOumU+JQxzro2pn4O8TpIi gPvbznFR1w3PRA== X-ME-Sender: X-Sasl-enc: 4HvT4lBj5QSjF7eGc6OK6V5Fk+9tvydWW7AvTCRUUTpV 1500235480 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 16 Jul 2017 16:03:46 -0400 Message-Id: <1500235468-15341-4-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1500235468-15341-1-git-send-email-cota@braap.org> References: <1500235468-15341-1-git-send-email-cota@braap.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.25 Subject: [Qemu-devel] [PATCH v2 03/45] cputlb: bring back tlb_flush_count under !TLB_DEBUG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Commit f0aff0f124 ("cputlb: add assert_cpu_is_self checks") buried the increment of tlb_flush_count under TLB_DEBUG. This results in "info jit" always (mis)reporting 0 TLB flushes when !TLB_DEBUG. Besides, under MTTCG tlb_flush_count is updated by several threads, so in order not to lose counts we'd either have to use atomic ops or distribute the counter, which is more scalable. This patch does the latter by embedding tlb_flush_count in CPUArchState. The global count is then easily obtained by iterating over the CPU list. Note that this change also requires updating the accessors to tlb_flush_count to use atomic_read/set whenever there may be conflicting accesses (as defined in C11) to it. Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Emilio G. Cota --- include/exec/cpu-defs.h | 1 + include/exec/cputlb.h | 3 +-- accel/tcg/cputlb.c | 17 ++++++++++++++--- accel/tcg/translate-all.c | 2 +- 4 files changed, 17 insertions(+), 6 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index bc8e7f8..e43ff83 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -137,6 +137,7 @@ typedef struct CPUIOTLBEntry { CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ + size_t tlb_flush_count; \ target_ulong tlb_flush_addr; \ target_ulong tlb_flush_mask; \ target_ulong vtlb_index; \ diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 3f94178..c91db21 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -23,7 +23,6 @@ /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); -extern int tlb_flush_count; - +size_t tlb_flush_count(void); #endif #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 85635ae..9377110 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -92,8 +92,18 @@ static void flush_all_helper(CPUState *src, run_on_cpu_f= unc fn, } } =20 -/* statistics */ -int tlb_flush_count; +size_t tlb_flush_count(void) +{ + CPUState *cpu; + size_t count =3D 0; + + CPU_FOREACH(cpu) { + CPUArchState *env =3D cpu->env_ptr; + + count +=3D atomic_read(&env->tlb_flush_count); + } + return count; +} =20 /* This is OK because CPU architectures generally permit an * implementation to drop entries from the TLB at any time, so @@ -112,7 +122,8 @@ static void tlb_flush_nocheck(CPUState *cpu) } =20 assert_cpu_is_self(cpu); - tlb_debug("(count: %d)\n", tlb_flush_count++); + atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); + tlb_debug("(count: %zu)\n", tlb_flush_count()); =20 tb_lock(); =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 090ebad..3ee69e5 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1916,7 +1916,7 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) atomic_read(&tcg_ctx.tb_ctx.tb_flush_count)); cpu_fprintf(f, "TB invalidate count %d\n", tcg_ctx.tb_ctx.tb_phys_invalidate_count); - cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); + cpu_fprintf(f, "TLB flush count %zu\n", tlb_flush_count()); tcg_dump_info(f, cpu_fprintf); =20 tb_unlock(); --=20 2.7.4