From nobody Tue Feb 10 04:03:45 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500040578220509.2577083872675; Fri, 14 Jul 2017 06:56:18 -0700 (PDT) Received: from localhost ([::1]:38141 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dW14p-00056R-1G for importer@patchew.org; Fri, 14 Jul 2017 09:56:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41092) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dW11K-0001GW-Ta for qemu-devel@nongnu.org; Fri, 14 Jul 2017 09:52:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dW11J-00018f-M2 for qemu-devel@nongnu.org; Fri, 14 Jul 2017 09:52:38 -0400 Received: from mx1.redhat.com ([209.132.183.28]:28729) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dW11J-00018P-D4 for qemu-devel@nongnu.org; Fri, 14 Jul 2017 09:52:37 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 3F61D80480; Fri, 14 Jul 2017 13:52:36 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.34.112.60]) by smtp.corp.redhat.com (Postfix) with ESMTP id 37CFC60608; Fri, 14 Jul 2017 13:52:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 3F61D80480 Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx04.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=imammedo@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 3F61D80480 From: Igor Mammedov To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 15:51:53 +0200 Message-Id: <1500040339-119465-3-git-send-email-imammedo@redhat.com> In-Reply-To: <1500040339-119465-1-git-send-email-imammedo@redhat.com> References: <1500040339-119465-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Fri, 14 Jul 2017 13:52:36 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH 02/28] mips: MIPSCPU model subclasses X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yongbok Kim , Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Aurelien Jarno , Eduardo Habkost Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Register separate QOM types for each mips cpu model, so it would be possible to reuse generic CPU creation routines. Signed-off-by: Igor Mammedov Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- CC: Aurelien Jarno CC: Yongbok Kim --- target/mips/cpu-qom.h | 2 ++ target/mips/cpu.h | 57 ++++++++++++++++++++++++++++++++++++++++= +++- target/mips/cpu.c | 51 +++++++++++++++++++++++++++++++++++++++ target/mips/translate.c | 13 +++++----- target/mips/translate_init.c | 57 ++--------------------------------------= ---- 5 files changed, 117 insertions(+), 63 deletions(-) diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index 3f5bf23..4b32401 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -35,6 +35,7 @@ #define MIPS_CPU_GET_CLASS(obj) \ OBJECT_GET_CLASS(MIPSCPUClass, (obj), TYPE_MIPS_CPU) =20 +typedef struct mips_def_t mips_def_t; /** * MIPSCPUClass: * @parent_realize: The parent class' realize handler. @@ -49,6 +50,7 @@ typedef struct MIPSCPUClass { =20 DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); + const mips_def_t *cpu_def; } MIPSCPUClass; =20 typedef struct MIPSCPU MIPSCPU; diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 9c32228..7c2e0bf 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -161,7 +161,62 @@ struct CPUMIPSMVPContext { #define CP0MVPC1_PCP1 0 }; =20 -typedef struct mips_def_t mips_def_t; +/* MMU types, the first four entries have the same layout as the + CP0C0_MT field. */ +enum mips_mmu_types { + MMU_TYPE_NONE, + MMU_TYPE_R4000, + MMU_TYPE_RESERVED, + MMU_TYPE_FMT, + MMU_TYPE_R3000, + MMU_TYPE_R6000, + MMU_TYPE_R8000 +}; + +struct mips_def_t { + const char *name; + int32_t CP0_PRid; + int32_t CP0_Config0; + int32_t CP0_Config1; + int32_t CP0_Config2; + int32_t CP0_Config3; + int32_t CP0_Config4; + int32_t CP0_Config4_rw_bitmask; + int32_t CP0_Config5; + int32_t CP0_Config5_rw_bitmask; + int32_t CP0_Config6; + int32_t CP0_Config7; + target_ulong CP0_LLAddr_rw_bitmask; + int CP0_LLAddr_shift; + int32_t SYNCI_Step; + int32_t CCRes; + int32_t CP0_Status_rw_bitmask; + int32_t CP0_TCStatus_rw_bitmask; + int32_t CP0_SRSCtl; + int32_t CP1_fcr0; + int32_t CP1_fcr31_rw_bitmask; + int32_t CP1_fcr31; + int32_t MSAIR; + int32_t SEGBITS; + int32_t PABITS; + int32_t CP0_SRSConf0_rw_bitmask; + int32_t CP0_SRSConf0; + int32_t CP0_SRSConf1_rw_bitmask; + int32_t CP0_SRSConf1; + int32_t CP0_SRSConf2_rw_bitmask; + int32_t CP0_SRSConf2; + int32_t CP0_SRSConf3_rw_bitmask; + int32_t CP0_SRSConf3; + int32_t CP0_SRSConf4_rw_bitmask; + int32_t CP0_SRSConf4; + int32_t CP0_PageGrain_rw_bitmask; + int32_t CP0_PageGrain; + int insn_flags; + enum mips_mmu_types mmu_type; +}; + +extern const struct mips_def_t mips_defs[]; +extern const int mips_defs_number; =20 #define MIPS_SHADOW_SET_MAX 16 #define MIPS_TC_MAX 5 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 82afdaa..111b5ae 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -151,12 +151,37 @@ static void mips_cpu_initfn(Object *obj) CPUState *cs =3D CPU(obj); MIPSCPU *cpu =3D MIPS_CPU(obj); CPUMIPSState *env =3D &cpu->env; + MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(obj); =20 cs->env_ptr =3D env; =20 if (tcg_enabled()) { mips_tcg_init(); } + + if (mcc->cpu_def) { + env->cpu_model =3D mcc->cpu_def; + } +} + +static char *mips_cpu_type_name(const char *cpu_model) +{ + return g_strdup_printf("%s-" TYPE_MIPS_CPU, cpu_model); +} + +static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) +{ + ObjectClass *oc; + char *typename; + + if (cpu_model =3D=3D NULL) { + return NULL; + } + + typename =3D mips_cpu_type_name(cpu_model); + oc =3D object_class_by_name(typename); + g_free(typename); + return oc; } =20 static void mips_cpu_class_init(ObjectClass *c, void *data) @@ -171,6 +196,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) mcc->parent_reset =3D cc->reset; cc->reset =3D mips_cpu_reset; =20 + cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; cc->do_interrupt =3D mips_cpu_do_interrupt; cc->cpu_exec_interrupt =3D mips_cpu_exec_interrupt; @@ -203,9 +229,34 @@ static const TypeInfo mips_cpu_type_info =3D { .class_init =3D mips_cpu_class_init, }; =20 +static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data) +{ + MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(oc); + mcc->cpu_def =3D data; +} + +static void mips_register_cpudef_type(const struct mips_def_t *def) +{ + char *typename =3D mips_cpu_type_name(def->name); + TypeInfo ti =3D { + .name =3D typename, + .parent =3D TYPE_MIPS_CPU, + .class_init =3D mips_cpu_cpudef_class_init, + .class_data =3D (void *)def, + }; + + type_register(&ti); + g_free(typename); +} + static void mips_cpu_register_types(void) { + int i; + type_register_static(&mips_cpu_type_info); + for (i =3D 0; i < mips_defs_number; i++) { + mips_register_cpudef_type(&mips_defs[i]); + } } =20 type_init(mips_cpu_register_types) diff --git a/target/mips/translate.c b/target/mips/translate.c index 7b3ae81..ae7ca80 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20193,16 +20193,15 @@ void mips_tcg_init(void) =20 MIPSCPU *cpu_mips_init(const char *cpu_model) { + ObjectClass *oc; MIPSCPU *cpu; - CPUMIPSState *env; - const mips_def_t *def; =20 - def =3D cpu_mips_find_by_name(cpu_model); - if (!def) + oc =3D cpu_class_by_name(TYPE_MIPS_CPU, cpu_model); + if (oc =3D=3D NULL) { return NULL; - cpu =3D MIPS_CPU(object_new(TYPE_MIPS_CPU)); - env =3D &cpu->env; - env->cpu_model =3D def; + } + + cpu =3D MIPS_CPU(object_new(object_class_get_name(oc))); =20 object_property_set_bool(OBJECT(cpu), true, "realized", NULL); =20 diff --git a/target/mips/translate_init.c b/target/mips/translate_init.c index c771ff1..16c214b 100644 --- a/target/mips/translate_init.c +++ b/target/mips/translate_init.c @@ -51,63 +51,9 @@ #define MIPS_CONFIG5 \ ((0 << CP0C5_M)) =20 -/* MMU types, the first four entries have the same layout as the - CP0C0_MT field. */ -enum mips_mmu_types { - MMU_TYPE_NONE, - MMU_TYPE_R4000, - MMU_TYPE_RESERVED, - MMU_TYPE_FMT, - MMU_TYPE_R3000, - MMU_TYPE_R6000, - MMU_TYPE_R8000 -}; - -struct mips_def_t { - const char *name; - int32_t CP0_PRid; - int32_t CP0_Config0; - int32_t CP0_Config1; - int32_t CP0_Config2; - int32_t CP0_Config3; - int32_t CP0_Config4; - int32_t CP0_Config4_rw_bitmask; - int32_t CP0_Config5; - int32_t CP0_Config5_rw_bitmask; - int32_t CP0_Config6; - int32_t CP0_Config7; - target_ulong CP0_LLAddr_rw_bitmask; - int CP0_LLAddr_shift; - int32_t SYNCI_Step; - int32_t CCRes; - int32_t CP0_Status_rw_bitmask; - int32_t CP0_TCStatus_rw_bitmask; - int32_t CP0_SRSCtl; - int32_t CP1_fcr0; - int32_t CP1_fcr31_rw_bitmask; - int32_t CP1_fcr31; - int32_t MSAIR; - int32_t SEGBITS; - int32_t PABITS; - int32_t CP0_SRSConf0_rw_bitmask; - int32_t CP0_SRSConf0; - int32_t CP0_SRSConf1_rw_bitmask; - int32_t CP0_SRSConf1; - int32_t CP0_SRSConf2_rw_bitmask; - int32_t CP0_SRSConf2; - int32_t CP0_SRSConf3_rw_bitmask; - int32_t CP0_SRSConf3; - int32_t CP0_SRSConf4_rw_bitmask; - int32_t CP0_SRSConf4; - int32_t CP0_PageGrain_rw_bitmask; - int32_t CP0_PageGrain; - int insn_flags; - enum mips_mmu_types mmu_type; -}; - /*************************************************************************= ****/ /* MIPS CPU definitions */ -static const mips_def_t mips_defs[] =3D +const mips_def_t mips_defs[] =3D { { .name =3D "4Kc", @@ -803,6 +749,7 @@ static const mips_def_t mips_defs[] =3D =20 #endif }; +const int mips_defs_number =3D ARRAY_SIZE(mips_defs); =20 static const mips_def_t *cpu_mips_find_by_name (const char *name) { --=20 2.7.4