From nobody Tue Feb 10 02:00:49 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500025499151295.1762400656364; Fri, 14 Jul 2017 02:44:59 -0700 (PDT) Received: from localhost ([::1]:36549 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVx9e-00024a-0E for importer@patchew.org; Fri, 14 Jul 2017 05:44:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34158) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVx7N-0008JK-U0 for qemu-devel@nongnu.org; Fri, 14 Jul 2017 05:42:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dVx7K-0000UB-RY for qemu-devel@nongnu.org; Fri, 14 Jul 2017 05:42:37 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:52940) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVx7K-0000Ta-De; Fri, 14 Jul 2017 05:42:34 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v6E9gT2d010086; Fri, 14 Jul 2017 11:42:29 +0200 Received: from localhost (unknown [31.210.188.120]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id 4479A5C8; Fri, 14 Jul 2017 11:42:24 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 12:42:23 +0300 Message-Id: <150002534291.22386.13499916738708680298.stgit@frigg.lan> X-Mailer: git-send-email 2.13.2 In-Reply-To: <150002001195.22386.4679134058536830996.stgit@frigg.lan> References: <150002001195.22386.4679134058536830996.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v6E9gT2d010086 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v13 22/26] target/arm: [tcg] Port to tb_stop X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova --- target/arm/translate.c | 165 +++++++++++++++++++++++++-------------------= ---- target/arm/translate.h | 1=20 2 files changed, 87 insertions(+), 79 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index c60be757dc..f221cbee5d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11967,7 +11967,7 @@ static target_ulong arm_tr_translate_insn(DisasCont= extBase *dcbase, assert(dc->base.num_insns =3D=3D 1); gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0), default_exception_el(dc)); - dc->base.is_jmp =3D DISAS_SKIP; + dc->base.is_jmp =3D DISAS_NORETURN; return dc->pc; } =20 @@ -12019,87 +12019,17 @@ static target_ulong arm_tr_translate_insn(DisasCo= ntextBase *dcbase, return dc->pc; } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { - DisasContext dc1, *dc =3D &dc1; - int max_insns; - - /* generate intermediate code */ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); + if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { return; } =20 - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - arm_tr_init_disas_context(&dc->base, cs); - - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_tr_tb_start(&dc->base, cs, &max_insns); - - do { - dc->base.num_insns++; - arm_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { - break; - } - } - } - - if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { - break; - } - } - - if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { - gen_io_start(); - } - - dc->base.pc_next =3D arm_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >=3D max_insns)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); - - if (dc->base.is_jmp !=3D DISAS_SKIP) { - if (tb->cflags & CF_LAST_IO) { - if (dc->condjmp) { - /* FIXME: This can theoretically happen with self-modifying - code. */ - cpu_abort(cs, "IO on conditional branch instruction"); - } - gen_io_end(); + if (dc->base.tb->cflags & CF_LAST_IO && dc->condjmp) { + /* FIXME: This can theoretically happen with self-modifying code. = */ + cpu_abort(cpu, "IO on conditional branch instruction"); } =20 /* At this stage dc->condjmp will only be set when the skipped @@ -12203,9 +12133,88 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) gen_goto_tb(dc, 1, dc->pc); } } +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext dc1, *dc =3D &dc1; + int max_insns; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cs, tb); + return; + } + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + arm_tr_init_disas_context(&dc->base, cs); + + + max_insns =3D tb->cflags & CF_COUNT_MASK; + if (max_insns =3D=3D 0) { + max_insns =3D CF_COUNT_MASK; + } + if (max_insns > TCG_MAX_INSNS) { + max_insns =3D TCG_MAX_INSNS; + } + + gen_tb_start(tb); + + tcg_clear_temp_count(); + arm_tr_tb_start(&dc->base, cs, &max_insns); + + do { + dc->base.num_insns++; + arm_tr_insn_start(&dc->base, cs); + + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { + CPUBreakpoint *bp; + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + if (bp->pc =3D=3D dc->base.pc_next) { + if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { + break; + } + } + } + + if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { + break; + } + } + + if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { + gen_io_start(); + } + + dc->base.pc_next =3D arm_tr_translate_insn(&dc->base, cs); + + if (tcg_check_temp_count()) { + fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", + dc->pc); + } + + if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || + dc->base.num_insns >=3D max_insns)) { + dc->base.is_jmp =3D DISAS_TOO_MANY; + } + } while (!dc->base.is_jmp); + + arm_tr_tb_stop(&dc->base, cs); + + if (dc->base.tb->cflags & CF_LAST_IO) { + gen_io_end(); } =20 -done_generating: gen_tb_end(tb, dc->base.num_insns); =20 #ifdef DEBUG_DISAS diff --git a/target/arm/translate.h b/target/arm/translate.h index 83e56dcb08..720cb102e3 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -149,7 +149,6 @@ static void disas_set_insn_syndrome(DisasContext *s, ui= nt32_t syn) * as opposed to attempting to use lookup_and_goto_ptr. */ #define DISAS_EXIT DISAS_TARGET_11 -#define DISAS_SKIP DISAS_TARGET_12 =20 #ifdef TARGET_AARCH64 void a64_translate_init(void);