From nobody Mon Feb 9 05:59:37 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1500024442942546.6786819142025; Fri, 14 Jul 2017 02:27:22 -0700 (PDT) Received: from localhost ([::1]:36472 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVwsa-0004J7-6B for importer@patchew.org; Fri, 14 Jul 2017 05:27:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59024) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVwrn-0003sK-5M for qemu-devel@nongnu.org; Fri, 14 Jul 2017 05:26:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dVwrh-0008Rm-EQ for qemu-devel@nongnu.org; Fri, 14 Jul 2017 05:26:31 -0400 Received: from roura.ac.upc.es ([147.83.33.10]:46406) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dVwrh-0008RG-2Z; Fri, 14 Jul 2017 05:26:25 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v6E9QL5r009614; Fri, 14 Jul 2017 11:26:21 +0200 Received: from localhost (unknown [31.210.188.120]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id 871E05C8; Fri, 14 Jul 2017 11:26:15 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Fri, 14 Jul 2017 12:26:14 +0300 Message-Id: <150002437386.22386.7745855254236101855.stgit@frigg.lan> X-Mailer: git-send-email 2.13.2 In-Reply-To: <150002001195.22386.4679134058536830996.stgit@frigg.lan> References: <150002001195.22386.4679134058536830996.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v6E9QL5r009614 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v13 18/26] target/arm: [tcg] Port to breakpoint_check X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson --- target/arm/translate.c | 53 +++++++++++++++++++++++++++++++-------------= ---- 1 file changed, 34 insertions(+), 19 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index b9183fc511..55bef09739 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11917,6 +11917,33 @@ static void arm_tr_insn_start(DisasContextBase *dc= base, CPUState *cpu) #endif } =20 +static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cp= u, + const CPUBreakpoint *bp) +{ + DisasContext *dc =3D container_of(dcbase, DisasContext, base); + + if (bp->flags & BP_CPU) { + gen_set_condexec(dc); + gen_set_pc_im(dc, dc->pc); + gen_helper_check_breakpoints(cpu_env); + /* End the TB early; it's likely not going to be executed */ + dc->base.is_jmp =3D DISAS_UPDATE; + } else { + gen_exception_internal_insn(dc, 0, EXCP_DEBUG); + /* The address covered by the breakpoint must be + included in [tb->pc, tb->pc + tb->size) in order + to for it to be properly cleared -- thus we + increment the PC here so that the logic setting + tb->size below does the right thing. */ + /* TODO: Advance PC by correct instruction length to + * avoid disassembler error messages */ + dc->pc +=3D 2; + dc->base.is_jmp =3D DISAS_NORETURN; + } + + return true; +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11965,28 +11992,16 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp; QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->pc) { - if (bp->flags & BP_CPU) { - gen_set_condexec(dc); - gen_set_pc_im(dc, dc->pc); - gen_helper_check_breakpoints(cpu_env); - /* End the TB early; it's likely not going to be e= xecuted */ - dc->base.is_jmp =3D DISAS_UPDATE; - } else { - gen_exception_internal_insn(dc, 0, EXCP_DEBUG); - /* The address covered by the breakpoint must be - included in [tb->pc, tb->pc + tb->size) in order - to for it to be properly cleared -- thus we - increment the PC here so that the logic setting - tb->size below does the right thing. */ - /* TODO: Advance PC by correct instruction length = to - * avoid disassembler error messages */ - dc->pc +=3D 2; - goto done_generating; + if (bp->pc =3D=3D dc->base.pc_next) { + if (arm_tr_breakpoint_check(&dc->base, cs, bp)) { + break; } - break; } } + + if (dc->base.is_jmp =3D=3D DISAS_NORETURN) { + break; + } } =20 if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) {