From nobody Tue Feb 10 09:28:21 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499810482698739.2268381455535; Tue, 11 Jul 2017 15:01:22 -0700 (PDT) Received: from localhost ([::1]:49118 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dV3Db-0007Mj-Sr for importer@patchew.org; Tue, 11 Jul 2017 18:01:19 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56392) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dV36O-0001Lm-Gl for qemu-devel@nongnu.org; Tue, 11 Jul 2017 17:53:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dV36N-0005Pp-CP for qemu-devel@nongnu.org; Tue, 11 Jul 2017 17:53:52 -0400 Received: from chuckie.co.uk ([82.165.15.123]:35140 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dV36N-0005PK-1W for qemu-devel@nongnu.org; Tue, 11 Jul 2017 17:53:51 -0400 Received: from host109-153-193-12.range109-153.btcentralplus.com ([109.153.193.12] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1dV36K-0003gf-CY; Tue, 11 Jul 2017 22:53:49 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Tue, 11 Jul 2017 22:53:27 +0100 Message-Id: <1499810007-28613-9-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1499810007-28613-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1499810007-28613-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.153.193.12 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 8/8] sun4u: move in-built devices behind PCI bridge A X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This switches the sun4u model to being much closer to a real Ultra 5. Since the existing code previously bypassed the PCI bridge interrupt swizzling, reorganise the interrupt mapping functions so that pci_pbm_map_irq() is used by the PCI bridges and pci_apb_map_irq() is used by the PCI host bridge. As part of this change we also combine the "onboard" NIC and the ebus into a single multi-function device as done on a real Ultra 5. Finally we mark the physically unavailable slots (plus slot 0 in busA) as reserved to ensure that users can't plug devices into non-existent slots which will break interrupt routing. Signed-off-by: Mark Cave-Ayland --- hw/pci-host/apb.c | 35 +++++++++++++++++++++++++++-------- hw/sparc64/sun4u.c | 25 ++++++++++++++++++++----- 2 files changed, 47 insertions(+), 13 deletions(-) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index f9badad..5000432 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -601,16 +601,35 @@ static uint64_t apb_pci_config_read(void *opaque, hwa= ddr addr, /* The APB host has an IRQ line for each IRQ line of each slot. */ static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num) { - return ((pci_dev->devfn & 0x18) >> 1) + irq_num; + /* Return the irq as swizzled by the PBM */ + return irq_num; } =20 static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num) { + PBMPCIBridge *br =3D PBM_PCI_BRIDGE(pci_bridge_get_device( + PCI_BUS(qdev_get_parent_bus(DEVICE(pci_dev))))); + int bus_offset; - if (pci_dev->devfn & 1) - bus_offset =3D 16; - else - bus_offset =3D 0; + if (br->busA) { + bus_offset =3D 0x0; + + /* The on-board devices have fixed (legacy) OBIO intnos */ + switch (PCI_SLOT(pci_dev->devfn)) { + case 1: + /* Onboard NIC */ + return 0x21; + case 3: + /* Onboard IDE */ + return 0x20; + + default: + /* Normal intno, fall through */ + break; + } + } else { + bus_offset =3D 0x10; + } return (bus_offset + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; } =20 @@ -692,7 +711,7 @@ PCIBus *pci_apb_init(hwaddr special_base, d =3D APB_DEVICE(dev); phb =3D PCI_HOST_BRIDGE(dev); phb->bus =3D pci_register_bus(DEVICE(phb), "pci", - pci_apb_set_irq, pci_pbm_map_irq, d, + pci_apb_set_irq, pci_apb_map_irq, d, &d->pci_mmio, get_system_io(), 0, 32, TYPE_PCI_BUS); @@ -726,14 +745,14 @@ PCIBus *pci_apb_init(hwaddr special_base, pci_dev =3D pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, TYPE_PBM_PCI_BRIDGE); br =3D PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(br, "pciB", pci_apb_map_irq); + pci_bridge_map_irq(br, "pciB", pci_pbm_map_irq); qdev_init_nofail(&pci_dev->qdev); *busB =3D pci_bridge_get_sec_bus(br); =20 pci_dev =3D pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, TYPE_PBM_PCI_BRIDGE); br =3D PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(br, "pciA", pci_apb_map_irq); + pci_bridge_map_irq(br, "pciA", pci_pbm_map_irq); qdev_prop_set_bit(DEVICE(pci_dev), "busA", true); qdev_init_nofail(&pci_dev->qdev); *busA =3D pci_bridge_get_sec_bus(br); diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 3bb3bf2..b8b96be 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -27,6 +27,7 @@ #include "cpu.h" #include "hw/hw.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_bus.h" #include "hw/pci-host/apb.h" #include "hw/i386/pc.h" #include "hw/char/serial.h" @@ -42,6 +43,7 @@ #include "hw/nvram/fw_cfg.h" #include "hw/sysbus.h" #include "hw/ide.h" +#include "hw/ide/pci.h" #include "hw/loader.h" #include "elf.h" #include "qemu/cutils.h" @@ -448,10 +450,17 @@ static void sun4uv_init(MemoryRegion *address_space_m= em, ivec_irqs =3D qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_M= AX); pci_bus =3D pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &p= ci_busA, &pci_busB, &pbm_irqs); - pci_vga_init(pci_bus); =20 - /* XXX Should be pci_busA */ - ebus =3D pci_create_simple(pci_bus, -1, "ebus"); + /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA = is + reserved (leaving no slots free after on-board devices) leaving slo= ts + 0-3 are free on busB 4*/ + pci_bus->slot_reserved_mask =3D 0xfffffffc; + pci_busA->slot_reserved_mask =3D 0xfffffff1; + pci_busB->slot_reserved_mask =3D 0xfffffff0; + + ebus =3D pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, "eb= us"); + qdev_init_nofail(DEVICE(ebus)); + isa_bus =3D pci_ebus_init(ebus, pbm_irqs); =20 i =3D 0; @@ -464,14 +473,20 @@ static void sun4uv_init(MemoryRegion *address_space_m= em, serial_hds_isa_init(isa_bus, i, MAX_SERIAL_PORTS); parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); =20 - pci_dev =3D pci_create(pci_bus, -1, "ne2k_pci"); + pci_dev =3D pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); + + pci_dev =3D pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), true, + "ne2k_pci"); dev =3D &pci_dev->qdev; qdev_set_nic_properties(dev, &nd_table[0]); qdev_init_nofail(dev); =20 ide_drive_get(hd, ARRAY_SIZE(hd)); =20 - pci_cmd646_ide_init(pci_bus, hd, 1); + pci_dev =3D pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); + qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); + qdev_init_nofail(&pci_dev->qdev); + pci_ide_create_devs(pci_dev, hd); =20 isa_create_simple(isa_bus, "i8042"); =20 --=20 1.7.10.4