From nobody Tue Feb 10 18:54:29 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499810148612918.9012589048618; Tue, 11 Jul 2017 14:55:48 -0700 (PDT) Received: from localhost ([::1]:49091 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dV38F-0002vQ-7G for importer@patchew.org; Tue, 11 Jul 2017 17:55:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56381) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dV36N-0001LS-0H for qemu-devel@nongnu.org; Tue, 11 Jul 2017 17:53:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dV36L-0005P2-VC for qemu-devel@nongnu.org; Tue, 11 Jul 2017 17:53:51 -0400 Received: from chuckie.co.uk ([82.165.15.123]:35138 helo=s16892447.onlinehome-server.info) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dV36L-0005OY-OG for qemu-devel@nongnu.org; Tue, 11 Jul 2017 17:53:49 -0400 Received: from host109-153-193-12.range109-153.btcentralplus.com ([109.153.193.12] helo=kentang.home) by s16892447.onlinehome-server.info with esmtpsa (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.76) (envelope-from ) id 1dV36H-0003gf-TZ; Tue, 11 Jul 2017 22:53:47 +0100 From: Mark Cave-Ayland To: qemu-devel@nongnu.org, atar4qemu@gmail.com Date: Tue, 11 Jul 2017 22:53:25 +0100 Message-Id: <1499810007-28613-7-git-send-email-mark.cave-ayland@ilande.co.uk> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1499810007-28613-1-git-send-email-mark.cave-ayland@ilande.co.uk> References: <1499810007-28613-1-git-send-email-mark.cave-ayland@ilande.co.uk> X-SA-Exim-Connect-IP: 109.153.193.12 X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk X-SA-Exim-Version: 4.2.1 (built Sun, 08 Jan 2012 02:45:44 +0000) X-SA-Exim-Scanned: Yes (on s16892447.onlinehome-server.info) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 82.165.15.123 Subject: [Qemu-devel] [PATCH 6/8] apb: add busA qdev property to PBM PCI bridge X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" As future sun4u PCI topologies place the ebus containing the in-built devic= es behind a PCI bridge, add a busA property to the PBM PCI bridge that is then used to allow IO accesses by default. This allows early fw_cfg/NVRAM/serial access to occur even before OpenBIOS has had a chance to configure the PCI bridges. Signed-off-by: Mark Cave-Ayland --- hw/pci-host/apb.c | 44 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 37 insertions(+), 7 deletions(-) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 5ad7678..f9badad 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -153,6 +153,18 @@ typedef struct APBState { unsigned int nr_resets; } APBState; =20 +#define TYPE_PBM_PCI_BRIDGE "pbm-bridge" +#define PBM_PCI_BRIDGE(obj) \ + OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE) + +typedef struct PBMPCIBridge { + /*< private >*/ + PCIBridge parent_obj; + + /* Is this busA with in-built devices (ebus)? */ + bool busA; +} PBMPCIBridge; + static inline void pbm_set_request(APBState *s, unsigned int irq_num) { APB_DPRINTF("%s: request irq %d\n", __func__, irq_num); @@ -634,8 +646,6 @@ static void pci_apb_set_irq(void *opaque, int irq_num, = int level) =20 static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) { - pci_bridge_initfn(dev, TYPE_PCI_BUS); - /* * command register: * According to PCI bridge spec, after reset @@ -645,11 +655,23 @@ static void apb_pci_bridge_realize(PCIDevice *dev, Er= ror **errp) * the reset value should be zero unless the boot pin is tied high * (which is true) and thus it should be PCI_COMMAND_MEMORY. */ - pci_set_word(dev->config + PCI_COMMAND, - PCI_COMMAND_MEMORY); + uint16_t cmd =3D PCI_COMMAND_MEMORY; + PBMPCIBridge *br =3D PBM_PCI_BRIDGE(dev); + + pci_bridge_initfn(dev, TYPE_PCI_BUS); + + /* If initialising busA, ensure that we allow IO transactions so that + we get the early serial console until OpenBIOS configures the bridg= e */ + if (br->busA) { + cmd |=3D PCI_COMMAND_IO; + } + + pci_set_word(dev->config + PCI_COMMAND, cmd); pci_set_word(dev->config + PCI_STATUS, PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM); + + pci_bridge_update_mappings(PCI_BRIDGE(br)); } =20 PCIBus *pci_apb_init(hwaddr special_base, @@ -702,16 +724,17 @@ PCIBus *pci_apb_init(hwaddr special_base, =20 /* APB secondary busses */ pci_dev =3D pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, - "pbm-bridge"); + TYPE_PBM_PCI_BRIDGE); br =3D PCI_BRIDGE(pci_dev); pci_bridge_map_irq(br, "pciB", pci_apb_map_irq); qdev_init_nofail(&pci_dev->qdev); *busB =3D pci_bridge_get_sec_bus(br); =20 pci_dev =3D pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, - "pbm-bridge"); + TYPE_PBM_PCI_BRIDGE); br =3D PCI_BRIDGE(pci_dev); pci_bridge_map_irq(br, "pciA", pci_apb_map_irq); + qdev_prop_set_bit(DEVICE(pci_dev), "busA", true); qdev_init_nofail(&pci_dev->qdev); *busA =3D pci_bridge_get_sec_bus(br); =20 @@ -833,6 +856,11 @@ static const TypeInfo pbm_host_info =3D { .class_init =3D pbm_host_class_init, }; =20 +static Property pbm_pci_properties[] =3D { + DEFINE_PROP_BOOL("busA", PBMPCIBridge, busA, false), + DEFINE_PROP_END_OF_LIST(), +}; + static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -848,12 +876,14 @@ static void pbm_pci_bridge_class_init(ObjectClass *kl= ass, void *data) set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->reset =3D pci_bridge_reset; dc->vmsd =3D &vmstate_pci_device; + dc->props =3D pbm_pci_properties; } =20 static const TypeInfo pbm_pci_bridge_info =3D { - .name =3D "pbm-bridge", + .name =3D TYPE_PBM_PCI_BRIDGE, .parent =3D TYPE_PCI_BRIDGE, .class_init =3D pbm_pci_bridge_class_init, + .instance_size =3D sizeof(PBMPCIBridge), }; =20 static void pbm_register_types(void) --=20 1.7.10.4