From nobody Wed Nov 5 09:04:12 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499788650066228.47024404517697; Tue, 11 Jul 2017 08:57:30 -0700 (PDT) Received: from localhost ([::1]:47133 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dUxXS-0004KR-H0 for importer@patchew.org; Tue, 11 Jul 2017 11:57:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39063) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dUxVp-0003Id-Iq for qemu-devel@nongnu.org; Tue, 11 Jul 2017 11:55:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dUxVo-0007CA-Ms for qemu-devel@nongnu.org; Tue, 11 Jul 2017 11:55:45 -0400 Received: from orth.archaic.org.uk ([81.2.115.148]:48438) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dUxVl-00077Y-0e; Tue, 11 Jul 2017 11:55:41 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.84_2) (envelope-from ) id 1dUxTe-0003KL-E6; Tue, 11 Jul 2017 16:53:30 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 11 Jul 2017 16:53:28 +0100 Message-Id: <1499788408-10096-4-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499788408-10096-1-git-send-email-peter.maydell@linaro.org> References: <1499788408-10096-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 81.2.115.148 Subject: [Qemu-devel] [PATCH 3/3] target/arm: Make Cortex-M3 and M4 default to 8 PMSA regions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Markus Armbruster , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The Cortex-M3 and M4 CPUs always have 8 PMSA MPU regions (this isn't a configurable option for the hardware). Make the default value of the pmsav7-dregion property be set per-cpu, so we don't need to have every user of these CPUs set it manually. (The existing default of 16 is correct for the other PMSAv7 core, the Cortex-R5.) Signed-off-by: Peter Maydell Reviewed-by: Marc-Andr=C3=A9 Lureau --- target/arm/cpu.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 28a9141..96d1f84 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -543,8 +543,15 @@ static Property arm_cpu_has_pmu_property =3D static Property arm_cpu_has_mpu_property =3D DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true); =20 +/* This is like DEFINE_PROP_UINT32 but it doesn't set the default value, + * because the CPU initfn will have already set cpu->pmsav7_dregion to + * the right value for that particular CPU type, and we don't want + * to override that with an incorrect constant value. + */ static Property arm_cpu_pmsav7_dregion_property =3D - DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 1= 6); + DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU, + pmsav7_dregion, + qdev_prop_uint32, uint32_t); =20 static void arm_cpu_post_init(Object *obj) { @@ -1054,6 +1061,7 @@ static void cortex_m3_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7); set_feature(&cpu->env, ARM_FEATURE_M); cpu->midr =3D 0x410fc231; + cpu->pmsav7_dregion =3D 8; } =20 static void cortex_m4_initfn(Object *obj) @@ -1064,6 +1072,7 @@ static void cortex_m4_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); cpu->midr =3D 0x410fc240; /* r0p0 */ + cpu->pmsav7_dregion =3D 8; } static void arm_v7m_class_init(ObjectClass *oc, void *data) { @@ -1112,6 +1121,7 @@ static void cortex_r5_initfn(Object *obj) cpu->id_isar4 =3D 0x0010142; cpu->id_isar5 =3D 0x0; cpu->mp_is_up =3D true; + cpu->pmsav7_dregion =3D 16; define_arm_cp_regs(cpu, cortexr5_cp_reginfo); } =20 --=20 2.7.4