From nobody Wed Nov 5 09:32:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499586932811631.5741814817007; Sun, 9 Jul 2017 00:55:32 -0700 (PDT) Received: from localhost ([::1]:35260 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dU73z-00083M-FE for importer@patchew.org; Sun, 09 Jul 2017 03:55:31 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46357) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dU6zJ-0004R9-6e for qemu-devel@nongnu.org; Sun, 09 Jul 2017 03:50:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dU6zE-0002zZ-0V for qemu-devel@nongnu.org; Sun, 09 Jul 2017 03:50:40 -0400 Received: from out3-smtp.messagingengine.com ([66.111.4.27]:46941) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1dU6zD-0002vF-O4 for qemu-devel@nongnu.org; Sun, 09 Jul 2017 03:50:35 -0400 Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 20BE5208C1; Sun, 9 Jul 2017 03:50:32 -0400 (EDT) Received: from frontend1 ([10.202.2.160]) by compute4.internal (MEProxy); Sun, 09 Jul 2017 03:50:32 -0400 Received: from localhost (flamenco.cs.columbia.edu [128.59.20.216]) by mail.messagingengine.com (Postfix) with ESMTPA id D90457E70C; Sun, 9 Jul 2017 03:50:31 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=braap.org; h=cc :date:from:in-reply-to:message-id:references:subject:to :x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=mesmtp; bh=OxC upJ9kaPIQ65jxY4EaWyWzBqgguQst3e6vw+DwxTM=; b=Mx2sNbhmWuWN/iU8NXa o+F1h0HhfGAkHykoYzJ3ohqsz+4pV+IvdYVwHub+7ZV4yRyGu7iH1n6eofDmT1NL kL2zto7LEGATzdXghqNJnzbC5HJAwc7FBrkRLvo5eEro9F71xQVI/8M3eJlokh6N 7f6oGOSHiW3Srwr+veOM8T1A= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:date:from:in-reply-to:message-id :references:subject:to:x-me-sender:x-me-sender:x-sasl-enc :x-sasl-enc; s=fm1; bh=OxCupJ9kaPIQ65jxY4EaWyWzBqgguQst3e6vw+Dwx TM=; b=cFmmewHXoejST1xlvnJtUQxHRv5vjmNCfG4ecacGXWf6R5tT/4yMv+UeS Ncze3vXJIaSgOKCyt25j0al0AmB10rFib/nRHxkgiZBNQybLHGzsJl3ei+tMoVom gGCTumBxOSTErprIRlFt4Jr7ydt8jccgcfqIT/+V4cmG6jNIFWXCK6J0pJhzwHlc PieCxRtPp05KdXNqtbjoBIfLnDnBmXJ3tI1fiWwhp+k90BVoaj7j5Oa4iYJiu9FZ cJ4vZ5v5SxscTVII3ZhnEVfOGyB07Z9nvqx69Nq/0TpCwHU7t3X1ikrmLjvJgVsM ftxn0XISHdVlSX68tchyD4vhQDrCg== X-ME-Sender: X-Sasl-enc: 7ejih04MB7R8yRco9qA+hISYhQkCa7k42wHevTtKYBen 1499586631 From: "Emilio G. Cota" To: qemu-devel@nongnu.org Date: Sun, 9 Jul 2017 03:49:55 -0400 Message-Id: <1499586614-20507-4-git-send-email-cota@braap.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1499586614-20507-1-git-send-email-cota@braap.org> References: <1499586614-20507-1-git-send-email-cota@braap.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 66.111.4.27 Subject: [Qemu-devel] [PATCH 03/22] cputlb: bring back tlb_flush_count under !TLB_DEBUG X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Commit f0aff0f124 ("cputlb: add assert_cpu_is_self checks") buried the increment of tlb_flush_count under TLB_DEBUG. This results in "info jit" always (mis)reporting 0 TLB flushes when !TLB_DEBUG. Besides, under MTTCG tlb_flush_count is updated by several threads, so in order not to lose counts we'd either have to use atomic ops or distribute the counter, which is more scalable. This patch does the latter by embedding tlb_flush_count in CPUArchState. The global count is then easily obtained by iterating over the CPU list. Signed-off-by: Emilio G. Cota Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson --- include/exec/cpu-defs.h | 1 + include/exec/cputlb.h | 3 +-- accel/tcg/cputlb.c | 17 ++++++++++++++--- accel/tcg/translate-all.c | 2 +- 4 files changed, 17 insertions(+), 6 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index bc8e7f8..e43ff83 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -137,6 +137,7 @@ typedef struct CPUIOTLBEntry { CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ + size_t tlb_flush_count; \ target_ulong tlb_flush_addr; \ target_ulong tlb_flush_mask; \ target_ulong vtlb_index; \ diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 3f94178..c91db21 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -23,7 +23,6 @@ /* cputlb.c */ void tlb_protect_code(ram_addr_t ram_addr); void tlb_unprotect_code(ram_addr_t ram_addr); -extern int tlb_flush_count; - +size_t tlb_flush_count(void); #endif #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 85635ae..9377110 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -92,8 +92,18 @@ static void flush_all_helper(CPUState *src, run_on_cpu_f= unc fn, } } =20 -/* statistics */ -int tlb_flush_count; +size_t tlb_flush_count(void) +{ + CPUState *cpu; + size_t count =3D 0; + + CPU_FOREACH(cpu) { + CPUArchState *env =3D cpu->env_ptr; + + count +=3D atomic_read(&env->tlb_flush_count); + } + return count; +} =20 /* This is OK because CPU architectures generally permit an * implementation to drop entries from the TLB at any time, so @@ -112,7 +122,8 @@ static void tlb_flush_nocheck(CPUState *cpu) } =20 assert_cpu_is_self(cpu); - tlb_debug("(count: %d)\n", tlb_flush_count++); + atomic_set(&env->tlb_flush_count, env->tlb_flush_count + 1); + tlb_debug("(count: %zu)\n", tlb_flush_count()); =20 tb_lock(); =20 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f768681..a936a5f 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1909,7 +1909,7 @@ void dump_exec_info(FILE *f, fprintf_function cpu_fpr= intf) atomic_read(&tcg_ctx.tb_ctx.tb_flush_count)); cpu_fprintf(f, "TB invalidate count %d\n", tcg_ctx.tb_ctx.tb_phys_invalidate_count); - cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); + cpu_fprintf(f, "TLB flush count %zu\n", tlb_flush_count()); tcg_dump_info(f, cpu_fprintf); =20 tb_unlock(); --=20 2.7.4