From nobody Wed Nov 5 09:30:27 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1499434759395994.9478684480409; Fri, 7 Jul 2017 06:39:19 -0700 (PDT) Received: from localhost ([::1]:56652 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTTTY-0004FR-UJ for importer@patchew.org; Fri, 07 Jul 2017 09:39:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59761) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTTM7-0007PF-Jh for qemu-devel@nongnu.org; Fri, 07 Jul 2017 09:31:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dTTM3-0004S0-Il for qemu-devel@nongnu.org; Fri, 07 Jul 2017 09:31:35 -0400 Received: from roura.ac.upc.edu ([147.83.33.10]:59994 helo=roura.ac.upc.es) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTTM2-0004RV-U9; Fri, 07 Jul 2017 09:31:31 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v67DVRkX022994; Fri, 7 Jul 2017 15:31:27 +0200 Received: from localhost (63.red-83-51-187.dynamicip.rima-tde.net [83.51.187.63]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id 72AF4258; Fri, 7 Jul 2017 15:31:21 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Fri, 7 Jul 2017 15:31:15 +0200 Message-Id: <149943427534.8972.12180811037907145821.stgit@frigg.lan> X-Mailer: git-send-email 2.13.2 In-Reply-To: <149942760788.8972.474351671751194003.stgit@frigg.lan> References: <149942760788.8972.474351671751194003.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v67DVRkX022994 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v12 27/27] target/arm: [tcg] Port to generic translation framework X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Signed-off-by: Llu=C3=ADs Vilanova --- target/arm/translate-a64.c | 120 ++++++----------------------------------= --- target/arm/translate.c | 124 +++++++---------------------------------= ---- target/arm/translate.h | 8 --- 3 files changed, 37 insertions(+), 215 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ea60d43a95..b569144ed9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11250,6 +11250,10 @@ static void aarch64_tr_init_disas_context(DisasCon= textBase *dcbase, init_tmp_a64_array(dc); } =20 +static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); @@ -11377,6 +11381,9 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) break; } } + + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next =3D dc->pc; } =20 static void aarch64_tr_disas_log(const DisasContextBase *dcbase, @@ -11389,107 +11396,12 @@ static void aarch64_tr_disas_log(const DisasCont= extBase *dcbase, 4 | (bswap_code(dc->sctlr_b) ? 2 : 0)); } =20 -void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, - TranslationBlock *tb) -{ - DisasContext *dc =3D container_of(dcbase, DisasContext, base); - int max_insns; - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - aarch64_tr_init_disas_context(&dc->base, cs); - - max_insns =3D dc->base.tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - - gen_tb_start(tb); - - tcg_clear_temp_count(); - - do { - dc->base.num_insns++; - aarch64_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - BreakpointCheckType bp_check =3D - aarch64_tr_breakpoint_check(&dc->base, cs, bp); - switch (bp_check) { - case BC_MISS: - /* Target ignored this breakpoint, go to next */ - break; - case BC_HIT_INSN: - /* Hit, keep translating */ - /* - * TODO: if we're never going to have more than one - * BP in a single address, we can simply use= a - * bool here. - */ - goto done_breakpoints; - case BC_HIT_TB: - /* Hit, end TB */ - goto done_generating; - default: - g_assert_not_reached(); - } - } - } - } - done_breakpoints: - - if (dc->base.num_insns =3D=3D max_insns && (dc->base.tb->cflags & = CF_LAST_IO)) { - gen_io_start(); - } - - dc->base.pc_next =3D aarch64_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabl= ed || - singlestep || dc->base.num_insns >=3D max_insn= s)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several time= s. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. - */ - } while (!dc->base.is_jmp); - - aarch64_tr_tb_stop(&dc->base, cs); - - if (dc->base.tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - -done_generating: - gen_tb_end(tb, dc->base.num_insns); - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - aarch64_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); - } -#endif - dc->base.tb->size =3D dc->pc - dc->base.pc_first; - dc->base.tb->icount =3D dc->base.num_insns; -} +const TranslatorOps aarch64_translator_ops =3D { + .init_disas_context =3D aarch64_tr_init_disas_context, + .tb_start =3D aarch64_tr_tb_start, + .insn_start =3D aarch64_tr_insn_start, + .breakpoint_check =3D aarch64_tr_breakpoint_check, + .translate_insn =3D aarch64_tr_translate_insn, + .tb_stop =3D aarch64_tr_tb_stop, + .disas_log =3D aarch64_tr_disas_log, +}; diff --git a/target/arm/translate.c b/target/arm/translate.c index 5db381491f..bb6be76696 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12131,6 +12131,9 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) gen_goto_tb(dc, 1, dc->pc); } } + + /* Functions above can change dc->pc, so re-align db->pc_next */ + dc->base.pc_next =3D dc->pc; } =20 static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) @@ -12142,116 +12145,29 @@ static void arm_tr_disas_log(const DisasContextB= ase *dcbase, CPUState *cpu) dc->thumb | (dc->sctlr_b << 1)); } =20 +static const TranslatorOps arm_translator_ops =3D { + .init_disas_context =3D arm_tr_init_disas_context, + .tb_start =3D arm_tr_tb_start, + .insn_start =3D arm_tr_insn_start, + .breakpoint_check =3D arm_tr_breakpoint_check, + .translate_insn =3D arm_tr_translate_insn, + .tb_stop =3D arm_tr_tb_stop, + .disas_log =3D arm_tr_disas_log, +}; + /* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb) { - DisasContext dc1, *dc =3D &dc1; - int max_insns; + DisasContext dc; + const TranslatorOps *ops =3D &arm_translator_ops; =20 - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ +#ifdef TARGET_AARCH64 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb =3D tb; - dc->base.pc_first =3D dc->base.tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; - arm_tr_init_disas_context(&dc->base, cs); - - - arm_tr_init_globals(&dc->base, cs); - max_insns =3D tb->cflags & CF_COUNT_MASK; - if (max_insns =3D=3D 0) { - max_insns =3D CF_COUNT_MASK; - } - if (max_insns > TCG_MAX_INSNS) { - max_insns =3D TCG_MAX_INSNS; - } - - gen_tb_start(tb); - - tcg_clear_temp_count(); - arm_tr_tb_start(&dc->base, cs); - - do { - dc->base.num_insns++; - arm_tr_insn_start(&dc->base, cs); - - if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { - CPUBreakpoint *bp; - QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { - if (bp->pc =3D=3D dc->base.pc_next) { - BreakpointCheckType bp_check =3D - arm_tr_breakpoint_check(&dc->base, cs, bp); - switch (bp_check) { - case BC_MISS: - /* Target ignored this breakpoint, go to next */ - break; - case BC_HIT_INSN: - /* Hit, keep translating */ - /* - * TODO: if we're never going to have more than one - * BP in a single address, we can simply use= a - * bool here. - */ - goto done_breakpoints; - case BC_HIT_TB: - /* Hit, end TB */ - goto done_generating; - default: - g_assert_not_reached(); - } - } - } - } - done_breakpoints: - - if (dc->base.num_insns =3D=3D max_insns && (tb->cflags & CF_LAST_I= O)) { - gen_io_start(); - } - - dc->base.pc_next =3D arm_tr_translate_insn(&dc->base, cs); - - if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", - dc->pc); - } - - if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep || - dc->base.num_insns >=3D max_insns)) { - dc->base.is_jmp =3D DISAS_TOO_MANY; - } - } while (!dc->base.is_jmp); - - arm_tr_tb_stop(&dc->base, cs); - - if (dc->base.tb->cflags & CF_LAST_IO) { - gen_io_end(); - } - -done_generating: - gen_tb_end(tb, dc->base.num_insns); - -#ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && - qemu_log_in_addr_range(dc->base.pc_first)) { - qemu_log_lock(); - qemu_log("----------------\n"); - arm_tr_disas_log(&dc->base, cs); - qemu_log("\n"); - qemu_log_unlock(); + ops =3D &aarch64_translator_ops; } #endif - tb->size =3D dc->pc - dc->base.pc_first; - tb->icount =3D dc->base.num_insns; + + translator_loop(ops, &dc.base, cpu, tb); } =20 static const char *cpu_mode_names[16] =3D { diff --git a/target/arm/translate.h b/target/arm/translate.h index 83e56dcb08..69d4b2f082 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -153,21 +153,15 @@ static void disas_set_insn_syndrome(DisasContext *s, = uint32_t syn) =20 #ifdef TARGET_AARCH64 void a64_translate_init(void); -void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu, - TranslationBlock *tb); void gen_a64_set_pc_im(uint64_t val); void aarch64_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); +extern const TranslatorOps aarch64_translator_ops; #else static inline void a64_translate_init(void) { } =20 -static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUStat= e *cpu, - TranslationBlock *tb) -{ -} - static inline void gen_a64_set_pc_im(uint64_t val) { }