From nobody Wed Nov 5 09:26:54 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 14994312390566.252109969458843; Fri, 7 Jul 2017 05:40:39 -0700 (PDT) Received: from localhost ([::1]:56262 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTSYm-0006hu-MK for importer@patchew.org; Fri, 07 Jul 2017 08:40:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43080) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTSWL-0004c0-Rh for qemu-devel@nongnu.org; Fri, 07 Jul 2017 08:38:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dTSWI-0005v5-Lv for qemu-devel@nongnu.org; Fri, 07 Jul 2017 08:38:05 -0400 Received: from roura.ac.upc.edu ([147.83.33.10]:43562 helo=roura.ac.upc.es) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dTSWI-0005up-8p; Fri, 07 Jul 2017 08:38:02 -0400 Received: from correu-1.ac.upc.es (correu-1.ac.upc.es [147.83.30.91]) by roura.ac.upc.es (8.13.8/8.13.8) with ESMTP id v67Cbvif021516; Fri, 7 Jul 2017 14:37:57 +0200 Received: from localhost (63.red-83-51-187.dynamicip.rima-tde.net [83.51.187.63]) by correu-1.ac.upc.es (Postfix) with ESMTPSA id 5909D456; Fri, 7 Jul 2017 14:37:52 +0200 (CEST) From: =?utf-8?b?TGx1w61z?= Vilanova To: qemu-devel@nongnu.org Date: Fri, 7 Jul 2017 14:37:46 +0200 Message-Id: <149943106604.8972.10208441394697288474.stgit@frigg.lan> X-Mailer: git-send-email 2.13.2 In-Reply-To: <149942760788.8972.474351671751194003.stgit@frigg.lan> References: <149942760788.8972.474351671751194003.stgit@frigg.lan> User-Agent: StGit/0.17.1-dirty MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by roura.ac.upc.es id v67Cbvif021516 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6.x [fuzzy] X-Received-From: 147.83.33.10 Subject: [Qemu-devel] [PATCH v12 14/27] target/arm: [tcg] Port to init_disas_context X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Peter Crosthwaite , "Emilio G. Cota" , "open list:ARM" , Paolo Bonzini , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Incrementally paves the way towards using the generic instruction translati= on loop. Signed-off-by: Llu=C3=ADs Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate.c | 86 +++++++++++++++++++++++++++-----------------= ---- 1 file changed, 48 insertions(+), 38 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 15b4fcb417..0179b1ce79 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11786,32 +11786,12 @@ static bool insn_crosses_page(CPUARMState *env, D= isasContext *s) return false; } =20 -/* generate intermediate code for basic block 'tb'. */ -void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +static void arm_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cs) { + DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUARMState *env =3D cs->env_ptr; ARMCPU *cpu =3D arm_env_get_cpu(env); - DisasContext dc1, *dc =3D &dc1; - target_ulong next_page_start; - int max_insns; - bool end_of_page; - - /* generate intermediate code */ - - /* The A64 decoder has its own top level loop, because it doesn't need - * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. - */ - if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { - gen_intermediate_code_a64(&dc->base, cs, tb); - return; - } - - dc->base.tb =3D tb; - dc->base.pc_first =3D tb->pc; - dc->base.pc_next =3D dc->base.pc_first; - dc->base.is_jmp =3D DISAS_NEXT; - dc->base.num_insns =3D 0; - dc->base.singlestep_enabled =3D cs->singlestep_enabled; =20 dc->pc =3D dc->base.pc_first; dc->condjmp =3D 0; @@ -11822,23 +11802,23 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) */ dc->secure_routed_to_el3 =3D arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb =3D ARM_TBFLAG_THUMB(tb->flags); - dc->sctlr_b =3D ARM_TBFLAG_SCTLR_B(tb->flags); - dc->be_data =3D ARM_TBFLAG_BE_DATA(tb->flags) ? MO_BE : MO_LE; - dc->condexec_mask =3D (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; - dc->condexec_cond =3D ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; - dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(tb->flags)); + dc->thumb =3D ARM_TBFLAG_THUMB(dc->base.tb->flags); + dc->sctlr_b =3D ARM_TBFLAG_SCTLR_B(dc->base.tb->flags); + dc->be_data =3D ARM_TBFLAG_BE_DATA(dc->base.tb->flags) ? MO_BE : MO_LE; + dc->condexec_mask =3D (ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) & 0xf) = << 1; + dc->condexec_cond =3D ARM_TBFLAG_CONDEXEC(dc->base.tb->flags) >> 4; + dc->mmu_idx =3D core_to_arm_mmu_idx(env, ARM_TBFLAG_MMUIDX(dc->base.tb= ->flags)); dc->current_el =3D arm_mmu_idx_to_el(dc->mmu_idx); #if !defined(CONFIG_USER_ONLY) dc->user =3D (dc->current_el =3D=3D 0); #endif - dc->ns =3D ARM_TBFLAG_NS(tb->flags); - dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(tb->flags); - dc->vfp_enabled =3D ARM_TBFLAG_VFPEN(tb->flags); - dc->vec_len =3D ARM_TBFLAG_VECLEN(tb->flags); - dc->vec_stride =3D ARM_TBFLAG_VECSTRIDE(tb->flags); - dc->c15_cpar =3D ARM_TBFLAG_XSCALE_CPAR(tb->flags); - dc->v7m_handler_mode =3D ARM_TBFLAG_HANDLER(tb->flags); + dc->ns =3D ARM_TBFLAG_NS(dc->base.tb->flags); + dc->fp_excp_el =3D ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); + dc->vfp_enabled =3D ARM_TBFLAG_VFPEN(dc->base.tb->flags); + dc->vec_len =3D ARM_TBFLAG_VECLEN(dc->base.tb->flags); + dc->vec_stride =3D ARM_TBFLAG_VECSTRIDE(dc->base.tb->flags); + dc->c15_cpar =3D ARM_TBFLAG_XSCALE_CPAR(dc->base.tb->flags); + dc->v7m_handler_mode =3D ARM_TBFLAG_HANDLER(dc->base.tb->flags); dc->cp_regs =3D cpu->cp_regs; dc->features =3D env->features; =20 @@ -11857,11 +11837,12 @@ void gen_intermediate_code(CPUState *cs, Translat= ionBlock *tb) * emit code to generate a software step exception * end the TB */ - dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(tb->flags); - dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(tb->flags); + dc->ss_active =3D ARM_TBFLAG_SS_ACTIVE(dc->base.tb->flags); + dc->pstate_ss =3D ARM_TBFLAG_PSTATE_SS(dc->base.tb->flags); dc->is_ldex =3D false; dc->ss_same_el =3D false; /* Can't be true since EL_d must be AArch64 = */ =20 + cpu_F0s =3D tcg_temp_new_i32(); cpu_F1s =3D tcg_temp_new_i32(); cpu_F0d =3D tcg_temp_new_i64(); @@ -11870,6 +11851,35 @@ void gen_intermediate_code(CPUState *cs, Translati= onBlock *tb) cpu_V1 =3D cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 =3D tcg_temp_new_i64(); +} + +/* generate intermediate code for basic block 'tb'. */ +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + CPUARMState *env =3D cs->env_ptr; + DisasContext dc1, *dc =3D &dc1; + target_ulong next_page_start; + int max_insns; + bool end_of_page; + + /* generate intermediate code */ + + /* The A64 decoder has its own top level loop, because it doesn't need + * the A32/T32 complexity to do with conditional execution/IT blocks/e= tc. + */ + if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) { + gen_intermediate_code_a64(&dc->base, cs, tb); + return; + } + + dc->base.tb =3D tb; + dc->base.pc_first =3D dc->base.tb->pc; + dc->base.pc_next =3D dc->base.pc_first; + dc->base.is_jmp =3D DISAS_NEXT; + dc->base.num_insns =3D 0; + dc->base.singlestep_enabled =3D cs->singlestep_enabled; + arm_tr_init_disas_context(&dc->base, cs); + next_page_start =3D (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PA= GE_SIZE; max_insns =3D tb->cflags & CF_COUNT_MASK; if (max_insns =3D=3D 0) {